Remote Droop Detection And Response Use Case
By Movellus - 28 Feb, 2024 - Comments: 0

While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialized and varied workloads. However, this asymmetry, combined with rapid provisioning changes, can lead to global voltage droops on the SoC resulting in potenti... » read more

Advanced Design Planning In IC Compiler II
By Synopsys - 28 Feb, 2024 - Comments: 0

By Rajiv Dave, CAE Manager, Synopsys. Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected from the ground up with the express focus to address the three key challenges of design planning: Capacity to handle the largest design optimally yet ... » read more

The Benefits Of Curvilinear Full-Chip Inverse Lithography Technology With Mask-Wafer Co-Optimization 
By Technical Paper Link - 27 Feb, 2024 - Comments: 0

A technical paper titled “Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization” was published by researchers at D2S and Micron. Abstract: "Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patte... » read more

Integration Challenges For RISC-V Designs
By Ed Sperling - 27 Feb, 2024 - Comments: 0

One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at ... » read more

Thinking Big: From Chips To Systems
By Ed Sperling - 27 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

Research Bits: Feb. 27
By Jesse Allen - 27 Feb, 2024 - Comments: 0

Phonon-magnon reservoir Researchers from TU Dortmund, Loughborough University, V. E. Lashkaryov Institute of Semiconductor Physics, and University of Nottingham were inspired by the human eye to propose an on-chip phonon-magnon reservoir for neuromorphic computing. In reservoir computing, input signals are mapped into a multidimensional space, which is not trained and only expedites recogni... » read more

New Issues In Power Semiconductors
By Ed Sperling - 26 Feb, 2024 - Comments: 0

The number of challenges is growing in power semiconductors, just as it is in traditional chips. Thermal dissipation and gradients, new design rules, and layout issues need to be considered, especially in the context of higher voltage and increased performance demands. Roland Jancke, design methodology head in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about issues in int... » read more

Backside Power Delivery Gears Up For 2nm Devices
By Laura Peters - 26 Feb, 2024 - Comments: 1

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

Chip Industry Week In Review
By The SE Staff - 23 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog IMC (IBM and ETH Zurich)
By Technical Paper Link - 22 Feb, 2024 - Comments: 0

A technical paper titled “A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing” was published by researchers at IBM Research Europe and IIS-ETH Zurich. Abstract: "Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference. However, a certain amount of digital post-processing is requ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy