Performing Multiple, Simultaneous Depositions In A High-Throughput, Multiplexing ALD/MLD-Style Reactor
By Technical Paper Link - 22 Feb, 2024 - Comments: 0

A technical paper titled “High throughput multiplexing reactor design for rapid screening of atomic/molecular layer deposition processes” was published by researchers at University of Washington. Abstract: "An approach is demonstrated for performing multiple, simultaneous depositions in a high-throughput, multiplexing atomic layer deposition/molecular layer deposition (ALD/MLD)-style reac... » read more

CMOS-Compatible, On-Chip, Compact And Wideband Nanoacoustic Pass-Band Filters For 5G And 6G
By Technical Paper Link - 22 Feb, 2024 - Comments: 0

A technical paper titled “Compact and wideband nanoacoustic pass-band filters for future 5G and 6G cellular radios” was published by researchers at Northeastern University. Abstract: "Over recent years, the surge in mobile communication has deepened global connectivity. With escalating demands for faster data rates, the push for higher carrier frequencies intensifies. The 7–20 GHz ran... » read more

Intel, And Others, Inside
By Ed Sperling - 22 Feb, 2024 - Comments: 2

Intel this week made a strong case for how it will regain global process technology leadership, unfurling an aggressive technology and business roadmap that includes everything from several more process node shrinks that ultimately could scale into the single-digit angstrom range to a broad shift in how it approaches the market. Both will be essential for processing the huge amount of data for ... » read more

UCIe Goes Back To The Drawing Board
By Gregory Haley - 22 Feb, 2024 - Comments: 0

The integration of multiple dies within a single package increasingly is viewed as the next evolution for extending Moore’s Law, but it also presents myriad challenges — particularly in achieving a universally accepted standard integrating plug-and-play chiplets from different vendors. “In some respects, people are already doing this,” says Debendra Das Sharma, Intel senior fellow an... » read more

Building CFETs With Monolithic And Sequential 3D
By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors
By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Utilizing Artificial Intelligence For Efficient Semiconductor Manufacturing
By Vivek Jain - 22 Feb, 2024 - Comments: 0

The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms, the complexity of the manufacturing process increases in response. It can take hundreds of process steps and more than a month to process a single wafer. It can subsequently take more than another month to go through the assembly, testing, and packaging st... » read more

Integrating Digital Twins In Semiconductor Operations
By Mark da Silva - 22 Feb, 2024 - Comments: 0

By Mark da Silva, Nishita Rao and Karim Somani Chipmakers must adopt transformative technologies including Digital Twins (DT) to keep pace with unprecedented global semiconductor industry growth that is expected to drive its total market value to $1 trillion[1] as soon as 2030. Leveraging predictive modeling and other efficiency-enhancing innovations, DTs promise to optimize semiconductor d... » read more

Make The Impossible Possible: Use Variable-Shaped Beam Mask Writers And Curvilinear Full-Chip Inverse Lithography Technology For 193i Contacts/Vias With Mask-Wafer Co-Optimization
By eBeam Initiative - 22 Feb, 2024 - Comments: 0

Abstract: "Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patterns in a reasonable write time. We jointly study and present the benefits of a full-chip, curvilinear, stitchless ILT with mask-wafer co-optimization (MWCO) for variable-shaped beam (VSB) mask writers and validate its benefits on mask and wafer at Micron Tec... » read more

Tackling Variability With AI-based Process Control
By Anne Meixner - 22 Feb, 2024 - Comments: 0

Jon Herlocker, co-founder and CEO of Tignis, sat down with Semiconductor Engineering to talk about how AI in advanced process control reduces equipment variability and corrects for process drift. What follows are excerpts of that conversation. SE: How is AI being used in semiconductor manufacturing and what will the impact be? Herlocker: AI is going to create a completely different factor... » read more

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