Die-To-Die Chiplet Communication


At CadenceLIVE Americas 2020, one of the most viewed videos was by Samsung Foundry's Kevin Yee and Cadence's Tom Wong, titled "Let’s Talk About Chips (Chiplets), Baby…It’s All About D2D!" They went for this title because it reminded them of the lyrics of an '80s song...which they proceeded to sing. Process and packaging trends Tom led off with a look at the trends in semiconducto... » read more

HBM2E Raises The Bar For AI/ML Training


The largest AI/ML neural network training models now exceed an enormous 100 billion parameters. With the rate of growth over the last decade on a 10X annual pace, we’re headed to trillion parameter models in the not-too-distant future. Given the tremendous value that can be derived from AI/ML (it is mission critical to five of six of the top market cap companies in the world), there has been ... » read more

MRAM Evolves In Multiple Directions


Magnetoresistive RAM (MRAM) is one of several new non-volatile memory technologies targeting broad commercial availability, but designing MRAM into chips and systems isn't as simple as adding other types of memory. MRAM isn’t an all-things-for-all-applications technology. It needs to be tuned for its intended purpose. MRAMs targeting flash will not do as well targeting SRAMs, and vice vers... » read more

Changing The Rules For Chip Scaling


Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

Nine Effective Features Of NVMe Verification IP For PCIe-Based SSD Storage


Non-Volatile Memory Express (NVMe) is a new software interface optimized for PCIe Solid State Drives (SSD). This paper provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to other conventional technologies, and point out key areas to focus on during its verification. You will learn how NVMe Questa Verification IP... » read more

Designing ASIPs With Confidence


Well-designed ASIPs with a strong SDK combine C/C++ programmability with the power and performance of dedicated hardware. Product families based on ASIP platforms are often highly flexible, capable of addressing multiple market segments with the same silicon and handling updates in the field. They lean well towards software-driven verification with few penalties for late product requirement cha... » read more

Multiband Active Antenna Tuner For Cellular IoT Applications


This white paper discusses related design challenges and solutions for developing a multiband active antenna tuner for cellular internet of things (IoT) massive machine-type communications (mMTC) applications. Click here to read more. » read more

Using 5nm Chips And Advanced Packages In Cars


Semiconductor Engineering sat down to discuss the impact of advanced node chips and advanced packaging on automotive reliability with Jay Rathert, senior director of strategic collaborations at KLA; Dennis Ciplickas, vice president of advanced solutions at PDF Solutions; Uzi Baruch, vice president and general manager of the automotive business unit at OptimalPlus; Gal Carmel, general manager of... » read more

Blog Review: March 10


Siemens EDA's Harry Foster checks out how the maturity of verification processes impact bug escapes in FPGA designs and whether safety critical development processes prevent bugs from escaping to silicon. Synopsys' Dennis Kengo Oka examines the weaknesses and vulnerabilities in automotive keyless entry systems and how security researchers hacked the Tesla Model X key fob. Cadence's Paul M... » read more

A Layered Approach To High Performance Device Virtualization


The complexity and performance requirements of computing systems have been growing and demands are further driven by applications, such as ML and the everything-connected world of IoT with many billions of connected devices. Arm has developed a virtualization and accelerator strategy to address this, which we discuss in this white paper from our Architecture and Technology Group A layered... » read more

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