category: Blogs – LPHP

category: IoT, Security & Automotive

A New Approach To Resistance Extraction For Unconventional Geometries
By Hossam Sarhan - 13 Dec, 2018 - Comments: 0

Unconventional metal structures have begun popping up in integrated circuits (ICs) with increasing regularity, for a number of reasons. The growing demand for integrated cameras and image recognition capabilities has fueled the need for components such as high-quality CMOS image sensors with low noise, high dynamic range, and low power. Technology scaling has also contributed to an increase in ... » read more

Taking Steps Toward Hybrid Memory
By Ken Wright - 13 Dec, 2018 - Comments: 0

What is the memory subsystem of the future, and how do we get there? Since our Hybrid Memory research program began, Rambus Labs and its industry partners and collaborators have made significant progress under the banner of OpenPOWER and OpenCAPI Foundations, an open development community based on the POWER microprocessor (mP) architecture. Rambus Labs is using the Wistron POWER9 systems’ Ope... » read more

Containing Design Complexity With POP IP
By Kelvin Low - 16 Nov, 2018 - Comments: 0

About 25 years ago, Carver Mead, one of the pioneers of VLSI design, told a technical audience then grappling with the complexities of quarter-micron design that he could see an evolutionary path to about 130nm, but after that point, the picture blurred. Flash forward to the present and we’re manufacturing SoCs at 7nm, and the output is truly amazing devices powering applications we and Me... » read more

Die-to-Die Interconnects for Chip Disaggregation
By Mondeep Thiara - 10 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increa... » read more

Die-To-Die Interconnects For Chip Disaggregation
By Mondeep Thiara - 09 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin... » read more

Aging Analysis Hits Mainstream
By Ann Mutschler - 08 Nov, 2018 - Comments: 1

Given the ever increasing challenge of designing high-reliability ICs – especially for automotive, medical, industrial, and aerospace and defense applications – the inclusion of aging analysis capabilities is on the rise in EDA tools as well as design IP. The issue comes down to predictability of devices as they operate. As discussed in, “Taming NBTI To Improve Device Reliability,” t... » read more

The Process Design Kit: Protecting Design Know-How
By John Ferguson - 08 Nov, 2018 - Comments: 2

Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each company. In these days, when designs contained hundreds of transistors, companies modeled each feature in an IC at a first principles level, meaning each transistor or fundamental device was analyzed an... » read more

Interaction Of Hard IP And Chip-Package
By Andy Heinig - 08 Nov, 2018 - Comments: 0

Current and future customer-specific circuit development requires an increasing number of different interfaces, such as for memory (DDR3, DDR4, LPDDR3, LPDDR4, etc.), radio interfaces (Bluetooth, NBIoT, etc.) or high-speed LVDS/SERDES interfaces (DisplayPort, Ethernet, USB, etc.). For customer-specific circuit projects, these components are frequently purchased as hard IP because the developmen... » read more

Next-Generation Ethernet Interconnects For 400G Hyperscale Data Centers
By Rita Horner - 08 Nov, 2018 - Comments: 0

The need for higher bandwidth with efficient connectivity increases as hyperscale data centers transition to faster, flatter, and more scalable network architectures, such as the 2-tier leaf-spine, as seen in Figure 1. The leaf-spine architecture requires massive interconnects as each leaf switch fans-out to every spine switch, maximizing connectivity between servers. Hardware accelerators, art... » read more

Psst, Says 5G… Wanna See What My New Antenna Tech Challenge Looks Like?
By Ronak Shah - 08 Nov, 2018 - Comments: 1

5G offers incredible potential, enabling 1000X more traffic, 10X faster speeds and an increase in the device battery capacity by 10X! So why hasn’t 5G technology been rolled out yet? The benefits all sound great, but there are also some challenges that need to be addressed. 5G is destined to cause a revolution around the world with burgeoning industries like autonomous driving, internet of... » read more

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