category: Blogs – LPHP

category: Auto, Security & Edge AI

AI, 5G, IoT Combine In The Fifth Wave Of Computing
By Simon Segars - 11 Jun, 2020 - Comments: 0

Something hugely positive is happening as a result of AI, 5G and the Internet of Things (IoT) reaching maturity at the same time. Like three kids growing up together, these technologies are feeding off each other’s energy and enhancing each other’s impact on the world. It’s this union, far greater than the sum of its parts, that I call the Fifth Wave of Computing. Why the fifth? We�... » read more

Models Built With Water
By Paul McLellan - 11 Jun, 2020 - Comments: 0

A couple of years ago I wrote a post using the famous quote by statistician George Box: All Models Are Wrong; Some Are Useful. In that post, I discussed paper and plastic airplanes, but mostly I talked about modeling in computers, and especially what I call the "digital illusion." The digital illusion is the idea that signals in digital chips are ones and zeros, with timing, and not analog vol... » read more

“See No Evil” Shouldn’t Apply To SoC Design
By Tim Penhale-Jones - 11 Jun, 2020 - Comments: 0

In the first part of this blog series, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. There’s a Japanese maxim, depicting three ‘wise’ monkeys… Kikazaru, Mizaru, and Iwazaru, better known as ‘hear no evil, see no evil and speak no evil’. If they we... » read more

Preventing Line Change Disruptions With Digital Twins
By Sameer Kher - 11 Jun, 2020 - Comments: 0

During times of crisis, companies can struggle to meet the demand for everyday necessities. Companies need to increase uptime without risking equipment or product quality. During times of crisis, like the COVID-19 pandemic, manufacturing companies can struggle to meet the demand of everyday necessities. We’ve seen this happen in real-time with the shortages of personal protective equipm... » read more

Introducing The Simulation World Virtual Conference For Multiphysics Verification
By Marc Swinnen - 22 May, 2020 - Comments: 0

The elimination of all live seminars and conferences has been felt particularly acutely by Ansys. The company’s extraordinary breadth of simulation products across many different physics – including fluidics, mechanical, optical, electrical, materials, and semiconductors – means that dozens of events for many different industrial sectors have been cancelled or postponed this year. In r... » read more

Remotely Performing IC Validation
By Tommy Mullane - 20 May, 2020 - Comments: 0

One of the key stages in designing any chip is the testing you do when you get the first silicon back. This is where you finally see the results of all your careful work and determine whether the chip is performing as designed, and as simulation told you it would. This is known as IC validation. The focus of validation is on functional test – checking that the chip in silicon meets the origin... » read more

Power Management And Integration Of IPs In SoCs: Part 2
By Progyna Khondkar - 14 May, 2020 - Comments: 0

Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

Layout Generators For Artificial Intelligence Hardware Design
By Benjamin Prautsch - 14 May, 2020 - Comments: 0

Artificial intelligence (AI) is a powerful tool that offers great convenience in many areas of life. In addition to improving Internet searches and online shopping, it enables driver assistance systems that can save lives, for example. AI in its various forms is the essential tool for such applications, and it can be expected to show a similar development as microelectronics did. Although AI... » read more

Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes
By Suresh Andani - 14 May, 2020 - Comments: 0

Conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA), that are demanded of leading-edge designs. With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is a growing challenge. In this context, disaggregated architectures such as chipl... » read more

The Need For 3D IC Packaging And Design Evolution
By Rita Horner - 14 May, 2020 - Comments: 0

If you are familiar with Moore’s Law, you’ve probably read pronouncements that the premise of transistor counts doubling each year is reaching a wall due to complex process technologies and device physics limitations. Regardless of how well transistor counts continue to scale, market segments continue to drive the thirst for more compute performance and fast time to markets. Artificial i... » read more

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