category: Blogs – LPHP

category: Auto, Security & Edge AI

IoT Debugging Crosses The Hardware-Software Divide
By Paul Hill - 09 Apr, 2020 - Comments: 0

By Paul Hill and Gordon MacNee Debugging is an important part of embedded design; one that necessarily crosses the hardware/software divide. At a system level, the functionality of an embedded design is increasingly defined by firmware, so avoiding bugs requires engineers with specific disciplines to work closely together during the design phase of a project. It can also mean resisting the u... » read more

Data Center Hyperscaling
By Stephen Crosher - 09 Apr, 2020 - Comments: 0

As we move in to 2020 it’s clear that every sector of industry, including the semiconductor industry, will have a responsibility to address growing environmental concerns. We should be aware that as our sector underpins the growth in AI, 5G telecommunications, crypto-currency and high performance compute applications, it is predicted that by 2030 energy consumption attributable to data center... » read more

Accelerated Life Testing For Failure Prediction
By Chris South - 09 Apr, 2020 - Comments: 0

By Theresa Duncan and Chris South Product reliability is essential for success, especially for electronic products like printed circuit boards (PCB). Accelerated life testing (ALT) is an expedient and cost-effective solution to determine the reliability and robustness of an electronic product or component. ALT uncovers potential failure risks and quantifies the life characteristics of a p... » read more

Easier Bond Finger Solder Mask Openings
By Tyler Lockman - 09 Apr, 2020 - Comments: 0

If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bond the wire to them, after all! We talked about general-purpose bounding shapes a few weeks ago in “A Boundless Bounty of Bounding Shapes”. Bond fingers have a... » read more

Simulation: Balancing Speed And Debug
By Rohit Narkar - 09 Apr, 2020 - Comments: 2

There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime performance never ebbs. Larger chips require more complex testbenches and much larger test suites since verification grows exponentially with increase in design size. With the diminishing return an... » read more

A New Era In Flexible, Affordable Design
By Phil Burr - 09 Apr, 2020 - Comments: 0

Socionext has always prided itself on flexibility. The company was formed in 2015 as part of the merger of the LSI businesses of Fujitsu and Panasonic. So not only did the company successfully merge engineering teams, it’s grown and expanded its offerings of advanced systems-on-chips (SoCs) over the years. As such, Socionext’s philosophy is rooted in doing more than just listening carefu... » read more

Packaging And Package Design For AI At The Edge
By Andy Heinig - 12 Mar, 2020 - Comments: 0

Industrial applications will acquire significantly more data directly from machines in coming years. To properly handle this increase in data, it must already be prepared at the machine. The data of the individual sensors can be processed, or an initial data merger can take place here at the so-called “edge.” Algorithms and methods from the field of artificial intelligence increasingly a... » read more

HBM2E Memory: A Perfect Fit For AI/ML Training
By Frank Ferro - 12 Mar, 2020 - Comments: 0

Artificial Intelligence/Machine Learning (AI/ML) growth proceeds at a lightning pace. In the past eight years, AI training capabilities have jumped by a factor of 300,000 (10X annually), driving rapid improvements in every aspect of computing hardware and software. Memory bandwidth is one such critical area of focus enabling the continued growth of AI. Introduced in 2013, High Bandwidth Memo... » read more

Demystifying Mirror Types
By Tyler Lockman - 12 Mar, 2020 - Comments: 0

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of mirroring which are used in different places. Often, I get questions about what, exactly, those differences are. And even more, why the styles are used for d... » read more

Die-to-Die Connectivity With High-Speed SerDes PHY IP
By Manuel Mota - 12 Mar, 2020 - Comments: 0

Hyperscale data center, artificial intelligence (AI), and networking SoCs have become more complex with advanced functionalities and have reached maximum reticle sizes. Designers are partitioning such SoCs in smaller modules requiring ultra- and extra-short reach links for inter-die connectivity with high data rates. The die-to-die connectivity must also ensure reliable links with extremely low... » read more

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