category: Power Source

category: IoT, Security & Automotive

The Next Steps
By Aveek Sarkar - 10 May, 2012 - Comments: 0

By Aveek Sarkar Remaining competitive in today’s semiconductor market means IC designers must meet performance, power and price targets for their design, regardless of the end application. Meeting these mutually conflicting goals requires enlisting the use of several architectural and design techniques, including three-dimensional (3D) or stacked-die architectures that can help meet perfo... » read more

Reliability Verification For Smart ICs
By Arvind Vel - 05 Apr, 2012 - Comments: 0

By Arvind Shanmugavel The electronic brains behind today’s advanced systems are smart ICs, paving the way for consumer electronics, energy, biomedical, automotive and avionics industries. Power efficiency and system integration are keys to the success of these smart systems. The IC industry has swiftly responded with state-of-the-art low-power techniques and chip integration initiatives f... » read more

A Smart System Technology Renaissance
By Margaret Schmitt - 09 Feb, 2012 - Comments: 0

By Margaret Schmitt Leonardo da Vinci invented fantastic machines to revolutionize how man would live, work, wage war, and travel. Describing how he conceived these designs he said, “A painter should begin every canvas with a wash of black, because all things in nature are dark except where exposed by the light.” We currently are experiencing a renaissance of our own, with the rise of s... » read more

Better Power Planning
By Preeti Gupta - 12 Jan, 2012 - Comments: 0

By Preeti Gupta Making the right architectural decisions for controlling power consumption and ensuring power integrity requires early identification and quantification of varying current demands in a semiconductor design. Furthermore, low-power designs pose complexities for power verification, such as significant current surges caused by clock gating or power gating transitions. In last mo... » read more

Power Delivery Networks
By Preeti Gupta - 01 Dec, 2011 - Comments: 0

By Preeti Gupta That power is now at the forefront of semiconductor design is no secret. It is also true that lowering power consumption drives product competitiveness and green technology—even more so in today’s mobile-driven market. But the same drive for lower power also increases the complexity of ensuring the power integrity of a system-on-chip (SoC). The power delivery network (PD... » read more

The Bigger Picture
By Aveek Sarkar - 02 Nov, 2011 - Comments: 0

By Aveek Sarkar IC power consumption is dependent on its supply voltage. To reduce power consumption, and heat dissipation, IC designers strive to design for lower supply voltages. But the threshold voltage that controls switching in digital CMOS devices hasn't scaled accordingly from reliability and other considerations. As the supply voltage reduces down close to the threshold voltage of ... » read more

Noise Coupling Analysis
By Arvind Vel - 06 Oct, 2011 - Comments: 0

By Arvind Shanmugaval Integrating digital and mixed-signal IP blocks in SoCs poses a considerable challenge to verification of power/ground and substrate noise. Traditional methods of power supply noise analysis are unable to meet the demands of today’s highly integrated designs with multiple low- power design techniques. Existing methods also do not provide sufficient capacity or the capabi... » read more

Picking The Right Models
By Various Writers - 08 Sep, 2011 - Comments: 0

By Ji Zheng As the focus on “efficient computing” increases and ICs are fabricated using process technologies that are more sensitive to voltage fluctuations, accurate modeling and prediction of chip-level, package-level and system-level behavior becomes a necessary design step. The use of chip macro models enables 3D-IC and IC-package-PCB co-analysis for power integrity, signal integrity,... » read more

New Stacking Issues
By Norman Chang - 11 Aug, 2011 - Comments: 0

Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome... » read more

Top 5 Reasons For Power Consumption Waste
By William Ruby - 21 Jul, 2011 - Comments: 0

By William Ruby Low-power seems to be on everyone’s mind these days, and it’s not just the chip design teams. One common consumer complaint is that the “battery life is way too short”! And of course, we all know this one, “OMG – that laptop is sure hot“! Even data center facilities managers lament, “We can’t supply enough power to the equipment—and when we do, we can’t co... » read more

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