Stacking The Deck


By Matt Elmore Can we finally say that 3D-IC design has emerged from the realm of theory and research to actual commercial implementation? Xilinx recently announced initial shipments of its Virtex-7 H580T FPGA, described as “The world’s first 3D heterogeneous all programmable product.” The benefits of 3D implementation are many, as are its challenges. One of the hottest 3D-IC topics t... » read more

New Reliability Issues


By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

The Next Steps


By Aveek Sarkar Remaining competitive in today’s semiconductor market means IC designers must meet performance, power and price targets for their design, regardless of the end application. Meeting these mutually conflicting goals requires enlisting the use of several architectural and design techniques, including three-dimensional (3D) or stacked-die architectures that can help meet perfo... » read more

Reliability Verification For Smart ICs


By Arvind Shanmugavel The electronic brains behind today’s advanced systems are smart ICs, paving the way for consumer electronics, energy, biomedical, automotive and avionics industries. Power efficiency and system integration are keys to the success of these smart systems. The IC industry has swiftly responded with state-of-the-art low-power techniques and chip integration initiatives f... » read more

A Smart System Technology Renaissance


By Margaret Schmitt Leonardo da Vinci invented fantastic machines to revolutionize how man would live, work, wage war, and travel. Describing how he conceived these designs he said, “A painter should begin every canvas with a wash of black, because all things in nature are dark except where exposed by the light.” We currently are experiencing a renaissance of our own, with the rise of s... » read more

Better Power Planning


By Preeti Gupta Making the right architectural decisions for controlling power consumption and ensuring power integrity requires early identification and quantification of varying current demands in a semiconductor design. Furthermore, low-power designs pose complexities for power verification, such as significant current surges caused by clock gating or power gating transitions. In last mo... » read more

Power Delivery Networks


By Preeti Gupta That power is now at the forefront of semiconductor design is no secret. It is also true that lowering power consumption drives product competitiveness and green technology—even more so in today’s mobile-driven market. But the same drive for lower power also increases the complexity of ensuring the power integrity of a system-on-chip (SoC). The power delivery network (PD... » read more

The Bigger Picture


By Aveek Sarkar IC power consumption is dependent on its supply voltage. To reduce power consumption, and heat dissipation, IC designers strive to design for lower supply voltages. But the threshold voltage that controls switching in digital CMOS devices hasn't scaled accordingly from reliability and other considerations. As the supply voltage reduces down close to the threshold voltage of ... » read more

Noise Coupling Analysis


By Arvind Shanmugaval Integrating digital and mixed-signal IP blocks in SoCs poses a considerable challenge to verification of power/ground and substrate noise. Traditional methods of power supply noise analysis are unable to meet the demands of today’s highly integrated designs with multiple low- power design techniques. Existing methods also do not provide sufficient capacity or the capabi... » read more

Picking The Right Models


By Ji Zheng As the focus on “efficient computing” increases and ICs are fabricated using process technologies that are more sensitive to voltage fluctuations, accurate modeling and prediction of chip-level, package-level and system-level behavior becomes a necessary design step. The use of chip macro models enables 3D-IC and IC-package-PCB co-analysis for power integrity, signal integrity,... » read more

← Older posts Newer posts →