category: Blogs – PTES

category: IoT, Security & Automotive

Untangling 3D NAND: Tilt, Registration, And Misalignment
By Kevin Heidrich - 09 Mar, 2021 - Comments: 0

The multiple demands of 3D NAND to enable yield and performance increase in difficulty at each generation. First generation devices, at 24-32 layer pairs, pushed process tools to extremes, going quickly from 10:1 to 40:1 aspect ratios for today’s 64-96 pair single tier devices. The aspect ratios increased as fast as the manufacturing challenges. To continue bit density scaling, processing imp... » read more

Finally, Analyzing All Test And Manufacturing Data Automatically
By Guy Cortez - 09 Mar, 2021 - Comments: 0

Product quality and yield, operational efficiency, and time-to-market continue to be dominant drivers in the semiconductor industry. Adding to this complexity is a diverse manufacturing and test supply-chain of independent providers all continuously generating enormous amounts of different types of chip-related data in various formats. The knowledge contained within this data is critical to pro... » read more

Demystifying ADC
By Xuandong Cao - 09 Feb, 2021 - Comments: 1

ADC stands for automatic defect classification. It’s a software that classifies defects based on image and metadata such as location, ROI, and other information associated with a defect. ADC is not a mysterious black box that’s impossible to understand. Instead, ADC classifies defects the same way a human operator does, by first being trained by an expert. Then, just like human classificati... » read more

A View Across The Siliconscape
By Stephen Crosher - 09 Feb, 2021 - Comments: 0

What would it look like if you had the magical ability to look inside a chip and cast your eyes across the tumultuous activities within the silicon itself? If you could gaze into the die and see the real-time peaks and troughs of voltage supply, stressed areas with high activity and heat and areas of calm where uneven workloads create idle processor cores. A vision of the chip landscape, seasca... » read more

Parallel RF Test For Next-Generation Communications
By Dieter Ohnesorge - 09 Feb, 2021 - Comments: 0

The test economics of state-of-the-art smartphones, tablets and routers demand highly parallel RF test. We are addressing this next wave in RF communications test, enabled by Wi-Fi 6E, operating in the 6GHz band and coming up to 7.125GHz. This forthcoming update to the Wi-Fi standard will extend the features and capabilities, including higher performance, lower latency, and faster data rates fo... » read more

Testing VCSEL Devices On-Wafer
By Dan Rishavy - 09 Feb, 2021 - Comments: 0

Vertical-Cavity Surface-Emitting Lasers, or VCSELs, are seeing unparalleled demand, thanks to new uses for them in smartphone and automotive applications. 3D sensing for facial recognition is the key application in smartphones, with up to three VCSEL dies being integrated into a single phone. Emerging automotive applications such as driver monitoring, infotainment control and LiDAR will provide... » read more

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible
By John Faase - 25 Jan, 2021 - Comments: 0

We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonl... » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

System-Level Test Methodologies Take Center Stage
By Fabio Pizza - 12 Jan, 2021 - Comments: 0

Because electronic systems for all applications in end-user markets must provide the highest possible reliability to match customers’ quality expectations, semiconductor components undergo multiple tests and stress steps to screen out defects that could arise during their lifecycle. Due to new semiconductor devices’ increasing design complexity and extreme process technology, increased test... » read more

Introduction To Test Data Formats
By Marie Ryan - 08 Dec, 2020 - Comments: 0

This blog is intended to provide an introduction to STDF and ATDF data formats. This is not intended to be definitive, only an introduction. If you are experienced with seeing data in spreadsheets and tables, then STDF is very different from what you are used to. Here we try to explain. STDF is the “Standard Test Data Format” developed jointly between some of the largest test equipment v... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy