category: Silicon Lifecycle Management

category: IoT, Security & Automotive

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy
By Ramsay Allen - 11 May, 2021 - Comments: 0

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Security For Cars That Are Smartphones On Wheels
By Taylor Amerding - 06 Apr, 2021 - Comments: 1

Your modern car is a computer on wheels—potentially hundreds of computers on a set of wheels. Heck, even the wheels are infested with computers—what do you think prompts that little light on your dashboard to come on if your tire pressure is low? And computers don’t just run your infotainment system, backup camera, dashboard warning lights, and the voice that tells you to buckle your seat... » read more

Finally, Analyzing All Test And Manufacturing Data Automatically
By Guy Cortez - 09 Mar, 2021 - Comments: 0

Product quality and yield, operational efficiency, and time-to-market continue to be dominant drivers in the semiconductor industry. Adding to this complexity is a diverse manufacturing and test supply-chain of independent providers all continuously generating enormous amounts of different types of chip-related data in various formats. The knowledge contained within this data is critical to pro... » read more

A View Across The Siliconscape
By Stephen Crosher - 09 Feb, 2021 - Comments: 0

What would it look like if you had the magical ability to look inside a chip and cast your eyes across the tumultuous activities within the silicon itself? If you could gaze into the die and see the real-time peaks and troughs of voltage supply, stressed areas with high activity and heat and areas of calm where uneven workloads create idle processor cores. A vision of the chip landscape, seasca... » read more

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible
By John Faase - 25 Jan, 2021 - Comments: 0

We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonl... » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Completing The Silicon Lifecycle Management Puzzle
By Stephen Crosher - 08 Dec, 2020 - Comments: 0

The year 2020 will be remembered for many reasons. The global pandemic, the political struggles and the extreme weather will occupy our thoughts for many years. There was another event that occurred in 2020 that will also be remembered in a smaller, but very important portion of the world. It’s the year that Synopsys acquired Moortec to complete the silicon lifecycle management (SLM) puzzle. ... » read more

Making IC Test Faster And More Accessible: Part 2
By Randy Fish - 11 Nov, 2020 - Comments: 0

Recently, my colleague Robert Ruiz described a new approach to scan test that utilizes the high-speed I/O (HSIO) ports that exist on most chips. The benefits of this new approach include reduced test time and cost thanks to the high-speed interface. Simplified pin electronics and tester setup are also benefits, as is the ability to run manufacturing tests in the field in support of silicon life... » read more

Making IC Test Faster And More Accessible: Part 1
By Robert Ruiz - 30 Oct, 2020 - Comments: 0

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

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