category: Blogs – SLD

category: IoT, Security & Automotive

Still Time to Blow Up UVM
By Neil Johnson - 28 Jan, 2016 - Comments: 2

Blowing up UVM is something I ran on my own blog a few years ago. Considering not much has changed with respect to UVM – that it continues to dominate verification circles – I figured it’s a discussion worth re-starting. In my mind, it’s not too late to take a few steps forward by blowing up UVM. A little history… the idea to blow up UVM was motivated by a slide snapshot posted to ... » read more

Device Adequateness
By Brian Bailey - 28 Jan, 2016 - Comments: 1

There is a growing chorus of people who are saying that 2016 will be, quite frankly, a boring technology year. They talk about no new or exciting products coming along. They talk about a lack of imagination, a lack of new product categories and quite a few failed categories from the past couple of years, such as wearables. It all comes down to the fact that products have not managed to make us ... » read more

Prototyping In The Driver’s Seat For ADAS Development
By Tom De Schutter - 28 Jan, 2016 - Comments: 1

Wikipedia describes ADAS (advanced driver assistance systems) as systems developed to automate/adapt/enhance vehicle systems for safety and better driving. Safety features are designed to avoid collisions and accidents by offering technologies that alert the driver to potential problems, or to avoid collisions by implementing safeguards and taking over control of the vehicle. Adaptive features ... » read more

DAC Finds A New Voice
By Mike Gianfagna - 28 Jan, 2016 - Comments: 1

DAC stands for Design Automation Conference. Everyone: please stop saying “the DAC conference”. This may not be as widespread as folks calling an automated teller machine an ATM machine, although it’s still odd. But I digress… This year, the 53rd DAC will be held in Austin, Texas starting June 5. I’ve been going to DAC for more years than I will ever put in writing. I’ve seen so... » read more

Three Steps To Complete Power-Aware Debug
By Ellie Burns - 28 Jan, 2016 - Comments: 0

In previous blogs, we’ve talked about UPF and the successive refinement low power flow developed by ARM and Mentor Graphics (you can find these here.) In this blog we’d like to walk through some typical debugging scenarios our customers face in their low power designs. So I’ve asked two of our low power debug experts, Gabriel Chidolue and Mark Handover, to join me to make sure you get ... » read more

Enablement For A Decade Of Innovation
By Frank Schirrmeister - 28 Jan, 2016 - Comments: 0

As I do every January, I am looking back 5, 10, and 15 years to see what predictions did and did not turn out to be right, and how that relates to design technologies enabling those developments. Looking back five years reveals just how key system-development technologies were for what IEEE dubbed the “Top 11 Technologies of the Decade”. Looking back 10 years shows how they enabled communic... » read more

Reprogrammable, Reprogrammable, Reprogrammable
By Aldec - 28 Jan, 2016 - Comments: 0

By Alex Grove I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree ... » read more

Announcing DAC’s First Art Show
By Chuck Alpert - 18 Jan, 2016 - Comments: 0

Every year DAC features something new. For the general chair, balancing tried and true conference elements with infusions of change is part of the art of putting on DAC and keeping it fresh. This year one change has to do with art itself — #53DAC features what I believe to be the first art show in the conference's long history. No, I'm not asking you to submit that painting you've been lab... » read more

Behind The Intel-Altera Deal
By Ed Sperling - 31 Dec, 2015 - Comments: 3

Intel completed its $16.7 billion acquisition of Altera this week, wrapping up what is arguably the semiconductor industry's most important M&A transaction of 2015. Time and numbers will tell exactly how important. There are two big challenges to making this deal work. One involves a big shift in direction away from simply shrinking features to include new architectures and packaging approac... » read more

How To Reduce Timing Closure Headaches
By Kurt Shuler - 22 Dec, 2015 - Comments: 0

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

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