Partitioning Processors For AI Workloads


Partitioning in complex chips is beginning to resemble a high-stakes guessing game, where choices need to extrapolate from what is known today to what is expected by the time a chip finally ships. Partitioning of workloads used to be a straightforward task, although not necessarily a simple one. It depended on how a device was expected to be used, the various compute, storage and data paths ... » read more

CXL: The Future Of Memory Interconnect?


Momentum for sharing memory resources between processor cores is growing inside of data centers, where the explosion in data is driving the need to be able to scale memory up and down in a way that roughly mirrors how processors are used today. A year after the CXL Consortium and JEDEC signed a memorandum of understanding (MOU) to formalize collaboration between the two organizations, suppor... » read more

Does Your NPU Vendor Cheat On Benchmarks?


It is common industry practice for companies seeking to purchase semiconductor IP to begin the search by sending prospective vendors a list of questions, typically called an RFI (Request for Information) or simply a Vendor Spreadsheet. These spreadsheets contain a wide gamut of requested information ranging from background on the vendor’s financial status, leadership team, IP design practices... » read more

Wireless Technology Insights: Navigating The Evolution From 5G To 6G


As 5G evolution advances, developments like the open radio access network (O-RAN) ecosystem, non-terrestrial network (NTN) infrastructure, and 5G reduced capability (RedCap) devices continue to gain momentum. Though 5G implementation is still underway, the wireless communication industry is already preparing for next-generation 6G wireless technology. With so much development happeni... » read more

Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?


By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

Automating Antenna Placement Workflow With PyAEDT


Antenna designs can reach daunting levels of complexity, and nowhere is that truer than in advanced 5G and 6G systems. One of the most difficult problems in this design space is signal degradation stemming from electromagnetic (EM) interaction between the phased array antenna and the host structure itself, such as a base station or satellites. It is a pernicious issue that takes several advance... » read more

Understand The Physics Of Re-Entry Vehicles Using Numerical Modeling And Simulation


In the early years of space exploration, scientists and engineers dreamed of sending vehicles to Mars that could land on the planet's surface and explore its terrain. However, one of their biggest challenges was safely reentering the Martian atmosphere. Many early attempts at Mars missions failed because the vehicles either burned up during re-entry or crashed onto the surface. However, as tech... » read more

The Value Of Field Solvers In Semiconductor Development Helps Drive Infineon Innovation


Parasitic extraction (PEX) helps ensure accurate circuit performance in the design and verification flow. Development of accurate PEX runsets depends on accurate and precise extraction results obtained using a full-featured field solver. Infineon selected the Calibre xACT 3D tool as their reference field solver tool of choice in the development of their next-generation semiconductor power produ... » read more

How Multi-Die Systems Are Transforming Electronic Design


How can the electronics industry continue as Moore’s law slows, system complexity increases, and the number of transistors balloons to trillions? Multi-die systems have emerged as the solution to go beyond Moore’s law and address the challenges of systemic complexity, allowing for accelerated, cost-effective scaling of system functionality, reduced risk and time to market, lower system p... » read more

Maximizing Design Flexibility For Multi-Layered And Diffractive Optical Components


A broad range of optical devices use nanostructured layers and surfaces to manipulate beams of light through diffraction and interference. Example devices include diffraction gratings, metasurfaces, diffractive optical elements, and metalenses. While the purpose and function of these devices can differ, they offer similar challenges from the point of view of simulation. In this white paper, ... » read more

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