Sustainable AI Systems For Energy-Efficient Computing


By Pushkar Apte, Jim Sexton, and Melissa Grupen-Shemansky The world is abuzz with the new opportunities being created by artificial intelligence (AI), enabled by the availability of unprecedented amounts of data. AI runs on the semiconductor engine, and in turn, creates a rising demand for semiconductor chips. The semiconductor industry is predicted to reach $1 trillion in revenue by 2030 ... » read more

Many Options For EUV Photoresists, No Clear Winner


In EUV lithography, and especially high-numerical-aperture EUV, balancing tradeoffs between resolution, sensitivity and line-width roughness is becoming increasingly difficult. Lithography patterning using extreme UV exposure depends on a resist mask that can simultaneously meet targets of small feature resolution, high sensitivity to EUV wavelength, and acceptable linewidth roughness. Unfor... » read more

Challenges Grow For Medical ICs


Demand for medical ICs used inside and outside the body is growing rapidly, but unique manufacturing and functional requirements coupled with low volumes have turned this into a complex and extremely challenging market. Few semiconductor applications demand this level of precision, reliability, and long-term stability. Unlike consumer electronics, where failure might mean a reboot or chip re... » read more

Linear Pluggable Optics Save Energy In Data Centers


Linear pluggable optics (LPO) is garnering more attention as a way to quickly and efficiently move data in and out of server racks, but a lack of standards for connecting the optical modules is slowing adoption at a time when there is growing pressure to reduce power in data centers. LPO is the newest of two approaches to solving the power wall problem in data centers. Co-packaged optics (CP... » read more

Back-End Packaging And Test: From Lessons Learned To Future Innovations


The semiconductor industry is a hallmark of technological innovation, evolving rapidly to meet the demands of an increasingly digital world. At its core, semiconductor manufacturing involves two main stages: front-end processes, (wafer fabrication) and back-end processes (packaging and test). Wafer fabrication consists of creating microscopic electronic circuits on a silicon wafer. Packaging an... » read more

Energy Saving In Semiconductor Packaging Plating Processes Through Chemical Deflashing Process Optimization


In response to the rising focus on sustainable manufacturing practices and corporate social responsibility, there has been a surge of interest in adopting environmentally friendly and green chemicals for semiconductor manufacturing processes. These alternatives aim to minimize hazards while promoting greater sustainability. Notably, this trend extends to exploring substitutes for conventional c... » read more

Speeding Up Computational Lithography With The Power And Parallelism Of GPUs


There are so many challenges in producing modern semiconductor devices that it’s amazing for the industry to pull it off at all. From the underlying physics to fabrication processes to the development flow, there is no shortage of tough issues to address. Some of the biggest arise in lithography for deep submicron chips. A recent post outlined the major trends in lithography and summarized a ... » read more

Advanced Packaging Evolution: Chiplet And Silicon Photonics-CPO


As we enter the AI era, the demand for enhanced connectivity in cloud services and AI computing continues to surge. With Moore’s Law slowing down, the increasing data rate requirements are surpassing the advancements of any single semiconductor technology. This shift underscores the importance of heterogeneous integration (HI) as a crucial solution for alleviating bandwidth bottlenecks. Tod... » read more

Interconnects Approach Tipping Point


As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Mechanical Stress In Semiconductor Development


With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,1 mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property de... » read more

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