category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

The Week In Review: Manufacturing
By Mark LaPedus - 16 Dec, 2016 - Comments: 0

Chipmakers Samsung is mulling over a plan to reorganize its System LSI division, according to a report from BusinessKorea. As part of the move, Samsung is mulling over the idea to spin off its foundry unit, according to the report. A spokeswoman for Samsung’s foundry unit said: “We don't have any comments on this story.” GlobalFoundries has added eight new partners to its FDXcelera... » read more

5 Takeaways from IEDM
By Mark LaPedus - 15 Dec, 2016 - Comments: 1

As usual, the recent IEEE International Electron Devices Meeting (IEDM) was a busy week. The event, which took place in San Francisco, featured a plethora of subjects, such as next-generation transistors and memories. The event also included tracks on non-traditional approaches like quantum and neuromorphic computing. And then, there were sessions on power semis and others. In no partic... » read more

Etching Technology Advances
By Jeff Dorsch - 15 Dec, 2016 - Comments: 0

Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

Inside Advanced Patterning
By Mark LaPedus - 15 Dec, 2016 - Comments: 0

Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at [getentity id="22817" e_name="Applied Materials"], sat down with Semiconductor Engineering to discuss the trends in patterning, selective processes and other topics. Raja is also a fellow at Applied Materials. What follows are excerpts of that conversion. SE: From your standpoint, what are the big... » read more

Using Automated Pattern Matching For SRAM Physical Verification
By Elven Huang - 15 Dec, 2016 - Comments: 0

How often have you struggled to verify static random-access memory (SRAM) blocks in your design? And how often, no matter how much time you spend on them, do they end up causing manufacturing issues? Memory is a critical component in today’s SoC designs, often consuming 50% or more of the die area. SRAM blocks are typically assembled in a layout using a set of specific intellectual propert... » read more

BEOL Issues At 10nm And 7nm (Part 1)
By Ed Sperling - 15 Dec, 2016 - Comments: 5

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Software Platforms Bridge The Design/Verification Gap For 5G Communications Design
By David Vye - 15 Dec, 2016 - Comments: 0

The integration of simulation technologies, system prototyping tools, and automated test equipment is critical for addressing the complexity of developing 5G wireless technology. In these cases, design teams will need to rely on a combination of simulation and prototype testing in order to ensure design robustness. Although simulation is essential to design a test bed or prototype, measurement... » read more

40nm Technology Reinvigorated
By Steve Sharp - 15 Dec, 2016 - Comments: 0

When selecting a foundry process for mobile consumer focused products, chip designers are considering the economics of the solution just as much as the technical specifications. Using the latest and greatest finFET process might get you performance headroom above your spec, but could cost significantly more than using a more established, proven process. Today’s 40nm CMOS processes have bee... » read more

Tech Talk: FD-SOI vs. FinFET
By Ed Sperling - 15 Dec, 2016 - Comments: 0

Jamie Schaeffer, 22FDX program director at GlobalFoundries, talks about the future of FD-SOI, what the tradeoffs are in performance, power and cost compared with finFETs, how many mask layers and patterning steps are required for each, and when 12nm FD-SOI will be introduced. Related Stories To 7nm And Beyond GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economi... » read more

BEOL Barricades Ahead
By David Fried - 15 Dec, 2016 - Comments: 0

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. Among the questions posed to panelists: What is BEOL? Where does it begin and end? Are there fundamental limits to interconnect processes? How much longer can we continue to use current interconnect processes and ... » read more

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