category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

Increasing The Conductive Density Of Packaging
By Shaun Bowers - 18 Feb, 2021 - Comments: 0

Wide bandgap (WBG) semiconductor technologies have created new challenges and opportunities for power packages. Developments such as silicon carbide (SiC) and gallium nitride (GaN), have a higher figure of merit (FOM) compared to silicon MOSFETs and have extended the efficiency, output power and/or switching frequency range and operating temperature range for power electronics. With lower lo... » read more

Packaging Demands For RF And Microwave Devices
By Ken Molitor - 18 Feb, 2021 - Comments: 1

RF and microwave integrated circuits (ICs), monolithic microwave ICs (MMICs) and systems in package (SiPs) are vital for a wide range of applications. These include mobile phones, wireless local-area networks (WLANs), ultra-wideband (UWB), internet-of-things (IoT), GPS and Bluetooth devices. Moreover, RF-optimized packaging products and processes are essential to enabling the 5G ramp-up. RFI... » read more

China Passes Americas And Japan In IC Capacity
By Christian Dieseldorff - 18 Feb, 2021 - Comments: 0

Back in 2012, China ranked fifth among seven regions worldwide in IC wafer capacity but surged past the Americas and Japan in 2018 and 2019 to claim the number three position (figure 1). That’s a big deal given that ICs account for the largest share of wafer capacity excluding discrete, opto, MEMS and sensors. China’s IC wafer capacity growth accelerated to tune of 14% in 2019 and 21% in... » read more

Power Converter Chip Research Booms
By Katherine Derbyshire - 18 Feb, 2021 - Comments: 0

Power electronics are booming, fueled by demand ranging from induction chargers for wearable and portable electronics, to charging stations for electric vehicles. An estimated 80% of all U.S. electricity will pass through some form of power converter by 2030, said Yogesh Ramadass, director of power management at Texas Instruments' Kilby Labs. Transportation applications, in particular, deman... » read more

Breaking The 2nm Barrier
By Mark LaPedus - 18 Feb, 2021 - Comments: 4

Chipmakers continue to make advancements with transistor technologies at the latest process nodes, but the interconnects within these structures are struggling to keep pace. The chip industry is working on several technologies to solve the interconnect bottleneck, but many of those solutions are still in R&D and may not appear for some time — possibly not until 2nm, which is expected t... » read more

WLFO For High-Performance Low-Cost Packaging Of RFMEMS-CMOS
By Amkor - 17 Feb, 2021 - Comments: 0

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging. Wafer-level fanout (W... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach
By Brewer Science - 17 Feb, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonstrat... » read more

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation
By Coventor - 17 Feb, 2021 - Comments: 0

In this paper, we explore an end-to-end solution using SEMulator3D to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in ter... » read more

Manufacturing Bits: Feb. 16
By Mark LaPedus - 16 Feb, 2021 - Comments: 0

Hybrid bonding consortium for packaging A*STAR’s Institute of Microelectronics (IME) and several companies have formed a new consortium to propel the development of hybrid bonding technology for chip-packaging applications. The group, called the Chip-to-Wafer (C2W) Hybrid Bonding Consortium, includes A*STAR’s IME organization, Applied Materials, ASM Pacific, Capcon, HD MicroSystems, ONT... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 12 Feb, 2021 - Comments: 0

Chipmakers The U.S. Semiconductor Industry Association (SIA) and several chip executives have sent a joint letter to President Biden, urging the administration to include substantial funding for semiconductor manufacturing and research in the U.S. As reported, the share of global semiconductor manufacturing capacity in the U.S. has decreased from 37% in 1990 to 12% today. “Semiconductors pow... » read more

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