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Power Converter Chip Research Booms

New materials, different approaches could have long-term impact for majority of electronics.


Power electronics are booming, fueled by demand ranging from induction chargers for wearable and portable electronics, to charging stagings for electric vehicles.

An estimated 80% of all U.S. electricity will pass through some form of power converter by 2030, said Yogesh Ramadass, director of power management at Texas Instruments’ Kilby Labs. Transportation applications, in particular, demand a challenging combination of high current density and high switching speeds, side by side with control logic that supports power conditioning, spike detection, and similar functions.

Silicon BCD (bipolar-CMOS-DMOS) is the incumbent technology for many of these applications. It merges bipolar elements for analog functions, CMOS for digital logic, and double-diffused metal oxide semiconductor (DMOS) for high-voltage elements. BCD offers a long list of desirable properties, including high density, high switching speed, good temperature stability, low Vt variation, and high yield, according to researcher Olivier Trescases and colleagues at the University of Toronto, speaking at December’s virtual IEEE Electron Device meeting.

Fig. 1: Silicon BCD platform. Source: STMicroelectronics

However, key parameters for power devices depend on the semiconductor bandgap. Wide-gap semiconductors serve high power density applications that silicon simply can’t.

Fig. 2: Bandgaps of potential semiconductors for power electronics. Sources: Wikipedia, IOPScience

In work presented at December’s Materials Research Society virtual meeting, Mark Hollis, group leader at MIT Lincoln Lab, and his colleagues looked at the relationship between critical field—the field at which avalanche breakdown occurs—and bandgap for wide-gap semiconductors. Values reported in the literature may use different doping levels, device designs, and testing conditions. The MIT group proposed a normalization relationship to allow comparisons between different designs and materials.

Equation 1:
Equation normalizing the critical field for different device designs.
Where PT and NPT refer to punch-through and non-punch-through devices, ND is the doping level, q is stored charge, W is device width, εcrit is critical field, and ε is permittivity. Using this relationship to normalize the available experimental data, they found a best-fit power law of:

εcrit ~ Eg1.86

A second important parameter, Baliga’s figure of merit, applies to devices at low frequencies where conduction losses dominate. It is defined in the next equation.

Equation 2: BFOM = permittivity x mobility x bandgap3

High frequency systems also must consider switching losses due to charging and discharging of the transistor’s input capacitance.

Why GaN?
Of the available candidate materials, GaN is attractive because it can be grown cost-effectively on silicon in a CMOS-compatible process, and offers high mobility with low parasitic capacitances. GaN deposition methods are reasonably well understood because the material is used in many solid-state lighting components. Trescases observed that GaN transistors can switch up to 600V at frequencies beyond 1MHz. As a result, it is becoming the dominant platform for high-frequency amplifiers and switches.

However, bonding wires between the GaN power devices and peripheral driver circuits, which are usually silicon, are often a bottleneck for high-frequency performance. Combining power devices and driver circuits in a single GaN component would potentially reduce parasitics and allow the incorporation of on-chip spike detection and other reliability enhancements.

Relative to silicon BCD, Trescases said that GaN process technology is much less mature, with much larger feature sizes. The risk of overstress is higher, too, due to the relatively small margin between the rated and maximum gate voltages. Only enhancement mode devices are available; there is no production-ready p-channel GaN device at this time. As a result, GaN circuits only can use resistor-transistor or directly-coupled FET logic, both of which consume relatively large amounts of static power and have relatively high gate leakage.

Kevin Chen, professor at Hong Kong University of Science and Technology’s Department of Electronic and Computer Engineering, explained in an IEDM presentation that there are two different commercially available GaN HEMT technologies. Both use a p-type GaN gate layer, with either an Ohmic or a Schottky-type gate, and the gate stacks are very different from silicon MOSFET designs. For example, the pGaN gate layer in a Schottky-type HEMT is floating. Charge stored in the gate layer causes the threshold voltage to shift dynamically as the switching transient is applied. The shift is intrinsic to the device, and not a sign of stress damage or poor quality. Still, it affects reverse conduction and requires a larger gate drive voltage to compensate.

What does “integration” entail?
Fully integrated GaN power circuits will need power transistors, as well as logic gates and passive elements. Trescases described five levels of integration. The most basic, “0” level, simply puts multiple power devices on a single substrate. This level requires an insulating substrate such as GaN on SOI for isolation, but otherwise it is not much more difficult to manufacture than discrete components. Level 1 adds gate drivers. These require only a few additional transistors and significantly reduce parasitic inductances. By reducing the risk of false turn-on, integrated drivers can improve device lifetime and thermal performance.

Level 2 integration, which adds sensing and level-shifting capability, supports more sophisticated signal conditioning circuits. These typically require less than 50 devices and less than 1% of the total power device circuit area. Level 2 integration also facilitates monitoring of device health, which is important for the extreme operating environments targeted by many proposed GaN applications.

Trescases believes that level 3 integration, adding on-chip auxiliary supplies, closed-loop sensing and protection circuits, will require substantial yield improvements and feature size reductions. Current GaN technology simply can’t make enough gates for closed-loop digital control. Similarly, level 4 integration, with advanced diagnostics and full closed-loop control, approaching what’s now available in Si-BCD, requires hundreds of logic gates. Trescases believes this is still years away. Moreover, current GaN circuits have high static power consumption and poor light-load efficiency, so this level of integration is probably not desirable for sub-50 W applications.

The Hong Kong group demonstrated steps toward complementary GaN logic, with a monolithic GaN CMOS inverter, a ring oscillator, and other components. They achieved switching speeds in the MHz, not GHz, range, with relatively large devices. Improvements in both performance and dimensions are likely. Because of the large mismatch between electron and hole mobilities in GaN, Chen said it’s not a good candidate for general-purpose CMOS logic. But it is very promising for logic control of power circuits. Combining GaN’s fast switching speed with SiC’s very mature support for high current densities also would be attractive.

Can monolithic silicon and GaN give the best of both?
Though projects like this are exciting, Han Wui Then, a components research engineer at Intel, said in an IEDM presentation that development of p-channel GaN devices is still fairly preliminary. In the meantime, p-channel silicon is an excellent complement to n-channel GaN, given its high hole and electron mobility. Combining the two into a single chip would reduce parasitics and improve signal integrity.

Like heterogeneous silicon integration, combining silicon and GaN devices complicates both manufacturing and design. Wafer-to-wafer bonding, for example, can connect pre-existing circuit blocks, but cost and design complexity may limit the potential interconnect density. Growth of polysilicon directly on GaN doesn’t require a template, and the silicon can be deposited after GaN transistor fabrication. While initial studies have found respectable device characteristics, the random orientation of polysilicon leads to substantial device variation.

Then’s group deposited epitaxial GaN on silicon, achieving 350GHz switching frequency and 1.7 mA/micron drain current, both of which are records for GaN NMOS on silicon. Unfortunately, silicon devices typically use the (100) surface, while GaN growth requires the (111) surface. The (111) silicon surface has worse mobility, and also has more interface states, degrading oxide reliability.

The best GaN quality is achieved with a fairly thick film, allowing formation of strain-relaxing dislocations between the GaN devices and the silicon. In the Intel process, however, thick layers are prone to thickness uniformity variations. It’s not yet clear, Then said, what kind of device density they’ll be able to achieve in practice.

Monolithic layer transfer, in contrast, decouples the two process technologies and design rules, bringing out the best in both materials. The Intel group transferred a blanket GaN layer with no devices, avoiding the alignment issues associated with wafer-to-wafer bonding.

Is the future of GaN the future of power electronics?
To displace silicon, GaN will need smaller feature sizes, more stable manufacturing processes, and reliable, high-yielding devices. Process development kits are still in their infancy, as well, Trescases said, “where Si-BCD was 15 years ago.” Right now, he said, GaN features “lightning fast power devices with heavily constrained supporting circuits, which makes circuit design very challenging.” For GaN power electronics to meet their potential, supporting circuits will need to catch up.

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