Return On Investment Of A Pre-Reflow AOI System


This paper describes the losses from defects at the placement process in the SMT line. Two case studies of European and Taiwanese SMT manufacturers illustrate the actual losses from their defects. An evaluation method to select a pre-reflow AOI system maximizing the return on investment (ROI) is introduced. In the end, ROIs of three commercial pre-reflow AOI systems are compared to demonstrate ... » read more

Doing More At Functional Test


Experts at the Table: Semiconductor Engineering sat down to discuss the increasing importance of functional test, especially in high-performance computing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center products); Nitza Basoco, tec... » read more

Overlay Optimization In Advanced IC Substrates


Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

IC Test And Quality Requirements Drive New Collaboration


Rapidly increasing chip and package complexity, coupled with an incessant demand for more reliability, has triggered a frenzy of alliances and working relationships that are starting to redefine how chips are tested and monitored. At the core of this shift is a growing recognition that no company can do everything, and that to work together will require much tighter integration of flows, met... » read more

Progress In Wafer And Package Level Defect Inspection


The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

New Strategies For Interpreting Data Variability


Every measurement counts at the nanoscopic scale of modern semiconductor processes, but with each new process node the number of measurements and the need for accuracy escalate dramatically. Petabytes of new data are being generated and used in every aspect of the manufacturing process for informed decision-making, process optimization, and the continuous pursuit of quality and yield. Most f... » read more

Using Automatic Defect Classification To Reduce The Escape Rate Of Defects


Automated optical inspection (AOI) is a cornerstone in semiconductor manufacturing, assembly and testing facilities, and as such, it plays a crucial role in yield management and process control. Traditionally, AOI generates millions of defect images, all of which are manually reviewed by operators. This process is not only time-consuming but error prone due to human involvement and fatigue, whi... » read more

Reimagining PVT Monitoring IP For Advanced Node GAA Process


As process technology continues to evolve, so must design tools and the IP that support them. One example of an industry evolution is on the PVT monitoring IP side. The process, voltage, and temperature (PVT) monitors embedded within chips provide feedback on silicon status at every stage of the lifecycle, including mission use in the field. The data gathered from the monitors enables benefits ... » read more

The Need For Speed: Wi-Fi 7 And The Era Of Ultra-Fast Internet


The exponential growth of data consumption and the proliferation of connected devices have driven the need for the development of Wi-Fi 7. With the increasing demand for high-speed internet access, especially in bandwidth-intensive applications such as streaming, gaming, and virtual reality, existing wireless standards have become inadequate to meet the evolving needs of users. Wi-Fi 7 addresse... » read more

Fabrication Of Vertical-Taper Structures For Silicon Photonic Devices By Using Local-Thickness-Thinning Process


Authors: Shunsuke Abe, Hideo Hara, Shin Masuda, and Hirohito Yamada. This paper describes a simple fabrication process of verticaltaper structures which can locally tune the thickness of silicon photonic devices. For low-loss spot-size conversion, taper angles less than 10° are required. To fabricate the gradual-slope shape of the vertical tapers, we have developed a step-andexposure lithog... » read more

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