Improving Reliability In Chips


Semiconductor Engineering sat down to discuss changes in test that address tracing device quality throughout a product’s lifetime with Tom Katsioulas, CEO at Archon Design Solutions and U.S. Department of Commerce IoT advisory board member; Ming Zhang, vice president of R&D Acceleration at PDF Solutions; and Uzi Baruch, chief strategy officer at proteanTecs. What follows are excerpts of t... » read more

Synopsys Timing Constraints Manager: Constraint Verification


Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no chan... » read more

proteanTecs On-Chip Monitoring And Deep Data Analytics System


High reliability applications in service-critical markets, such as autonomous driving and cloud computing, demand maximum performance and minimal power and cost. Reducing design margins while maintaining high reliability becomes imperative. State-of-the-art silicon processes offer mainly logic density improvements at limited speedup. Worst-case design analysis is not cost effective anymore. ... » read more

Chip Industry Week In Review


By Liz Allan, Jesse Allen, and Karen Heyman Global semiconductor equipment billings dipped 2% year-over-year to US$25.8 billion in Q2, and slipped 4% compared with Q1, according to SEMI. Similarly, the top 10 semiconductor foundries reported a 1.1% quarterly-over-quarter revenue decline in Q2. A rebound is anticipated in Q3, according to TrendForce. Synopsys extended its AI-driven EDA ... » read more

Manual X-ray Inspection


Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

Navigating the Metrology Maze For GAA FETs


The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

SiC Growth For EVs Is Stressing Manufacturing


The electrification of vehicles is fueling demand for silicon carbide power ICs, but it also is creating challenges in finding and identifying defects in those chips. Coinciding with this is a growing awareness about just how immature SiC technology is and how much work still needs to be done — and how quickly that has to happen. Automakers are pushing heavily into electric vehicles, and t... » read more

Using Generative AI To Connect Lab To Fab Test


Executive Insight: Thomas Benjamin, CTO at National Instruments, sat down with Semiconductor Engineering to discuss a new way of looking at test, using data as a starting point and generative AI as a bridge between different capabilities. SE: What are the big changes you're seeing and how is that affecting movement of critical data from the lab to the fab? Benjamin: If you walk into any m... » read more

3D NAND Needs 3D Metrology


By Nick Keller and Andy Antonelli You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle. Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production. However, there are challenges... » read more

The Importance Of Efficient Low Power Validation In Electronics


In the fast-paced world of electronics, innovation is driven not only by cutting-edge features but also by energy efficiency. Low power validation has emerged as a critical aspect of electronics applications, playing a pivotal role in designing devices that are both sustainable and user-friendly. The rise of the Internet of Things (IoT) and wearable technologies has transformed the way we inter... » read more

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