Why Thin Film Measurements Matter


Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices. Whether it’s the read and writ... » read more

Shift Left In DFT Design


The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to maintain high productivity and quality throughout the design flow. This keeps projects on schedule, within budget, and ensures they remain high-quality, reliable, yield well and perform as intended. ... » read more

2025-Product Design Enhancement With Test Structures For Non-Contact Detection Of Yield Detractors


Abstract: Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction... » read more

Improving Manufacturing Yields With Process Control Solutions


Even after 20 years or so, process control continues to be a confusing or misunderstood technology. A short description of process control is an accurate one—It’s a means of controlling manufacturing equipment and reducing variability to improve yields and performance of the products manufactured through that equipment. Tools like PDF Solutions Fault Detection and Classification (FDC)... » read more

Nearly Invisible: Defect Detection Below 5nm


Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Optimizing Tester Memory Resources With Pooling Technology


The rapid evolution of semiconductor devices has amplified the demand for advanced automated test equipment (ATE) that can handle increasingly complex test scenarios for logic devices. ATE vector memory is becoming an increasingly valuable commodity as scan-pattern volume soars. Extrapolations based on data from the International Technology Roadmap for Semiconductors (ITRS) indicate that scan d... » read more

Hunting For Macro Defects


Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the wafer level, a macro-defect can affect more than one die, and in some cases large regions of a wafer. Finding macro defects can indicate a significant issue with a process module, a particular fi... » read more

A Universal Deep Learning Model For Segmenting Automated Optical Inspection Images


A new technical paper titled "A Universal AI-Powered Segmentation Model for PCBA and Semiconductor" was published by researchers at Nordson Corporation. "This paper introduces a novel universal deep learning model designed to segment AOI images for both PCBA and 17 semiconductor components, offering a more robust and adaptable solution for defect detection," states the paper. Read more he... » read more

Need For KGD Drives Singulated Die Screening


The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly higher than with a single die. Better methods for inspecting and testing these devices are already starting to roll out. High-throughput infrared inspection is capable of catching more sub-surface d... » read more

Chip Failures: Prevention And Responses Over Time


Experts at the Table: Semiconductor Engineering sat down to discuss the causes of chip failures, how to respond to them, and how that can change over time, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, hi... » read more

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