Challenges In Using Sub-7nm ICs In Automotive


The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge. Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over... » read more

Can Your ATPG Do This? Cut Defects Escaping Detection With ML


Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the silicon and ensures they are applied effectively using the chip’s Design-for-Test (DFT) infrastructure. This combination enhances fault detection while optimizing test efficiency. These patter... » read more

Rethinking Chip Reliability For Harsh Conditions


As semiconductors push into environments once considered untenable, reliability expectations are being redefined. From the vacuum of space and the inside of jet engines to deep industrial automation and electrified drivetrains, chips now must endure extreme temperature swings, corrosive atmospheres, mechanical vibration, radiation, and unpredictable power cycles, all while delivering increasing... » read more

High-Quality Data Needed To Better Utilize Fab Data Streams


Fab operations have wrestled with big data management issues for decades. Standards help, but only if sufficient attention to detail is taken during collection. Semiconductor wafer manufacturing represents one of the most complex manufacturing processes in the world. With each generation of process improvement comes more sophisticated fab equipment, new process recipes, and exponential incre... » read more

The Data Dilemma In Semiconductor Testing And Why It Matters: Part 1


In today’s semiconductor industry, machine learning (ML) is no longer a buzzword — it’s an operational necessity. From optimizing test flows to identifying device drifts and executing advanced analytics like VMIN or trimming, ML-based applications are increasingly used to boost yields, improve quality, and lower test costs. But there’s a catch. To make these intelligent applications ... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity


Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

Problems In Testing AI Chips


As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging


The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

AI For Test: The New Frontier


Dr. Ming Zhang, PDF Solutions vice president of Fabless Solutions, delivered the keynote at the TestConX 2025 conference in March. As he began his presentation, Ming borrowed the “learn, explore and share” line from Ira Feldman, the organizer of the conference, to set the tone of his talk. He promised to share what he and PDF Solutions learned and what’s useful and what’s not useful as ... » read more

Better ATPG To Minimize Chip Test Time And Cost


As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

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