category: Test, Measurement and Analytics

category: IoT, Security & Automotive

AI Semiconductors Require An Integrated Test Solution
By Ira Leventhal - 11 Mar, 2025 - Comments: 0

The rapid proliferation of generative pre-trained transformers based on large language models (LLMs) is driving growth in the market for chips that can run the LLMs and other artificial intelligence (AI) and machine learning (ML) applications. Several types of chips hold promise for accelerating AI computing. Graphical processing units (GPUs) have proven to be capable solutions for the server/c... » read more

Failure To Launch
By Gregory Haley - 11 Mar, 2025 - Comments: 1

Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems. Traditional failure analysis techniqu... » read more

Full-Chip Voltage Contrast Inference Using Deep Learning; You Only Look Once: Voltage Contrast (YOLO-VC)
By PDF Solutions - 11 Mar, 2025 - Comments: 0

Abstract: The electron beam inspection methodology for voltage contrast (VC) defects has been widely adopted in the early stages of sub-10nm logic and memory technology development, as well as in new product introductions. However, due to throughput limitations, full-chip inspection at the 300mm wafer scale remains impractical for yield ramp and production applications. To address this challeng... » read more

Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

Optimizing DFT With AI And BiST
By Gregory Haley - 12 Feb, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. Wh... » read more

Innovations Driving The Advanced Packaging Roadmap: Part Two
By Keith Best - 11 Feb, 2025 - Comments: 0

As the advanced packaging world enters the AI era, manufacturers are exploring ways to extend the life cycle of organic substrates and successfully introduce glass substrates to high volume manufacturing. In last month’s blog, “Innovations Driving The Advanced Packaging Roadmap: Part One,” we discussed the challenges of organic and glass substrates as the industry marches toward sub-2µm ... » read more

Transformational Opportunities Coming To Semiconductor Manufacturing
By John Kibarian - 11 Feb, 2025 - Comments: 0

During the GSA US Executive Forum in September 2024, a panel discussion brought together Marco Chisari, EVP from Samsung Semiconductor, Jeff Howell, Global VP for High Tech at SAP, and John Kibarian, CEO of PDF Solutions. The purpose of the discussion was to compare and contrast the perspectives from one of the largest global semiconductor companies with that of the most widely used enterpri... » read more

Hyperconvergence Of Design For Test And Physical Design
By Sri Ganta - 11 Feb, 2025 - Comments: 0

By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

Silent Data Errors Still Slipping Through The Cracks
By Laura Peters - 11 Feb, 2025 - Comments: 0

Silent data corruption errors in large server farms have become a major concern of cloud users, hyperscalers, processor manufacturers and the test community. Silent data errors (also called silent data corruption errors) are hardware errors that occur when an incorrect computational result from a processor core goes undetected by the system. The data is silently corrupted because neither sof... » read more

Simulation Closes Gap Between Chip Design Optimization And Manufacturability
By Gregory Haley - 11 Feb, 2025 - Comments: 0

Simulation is playing an increasingly critical and central role throughout the design-through-manufacturing flow, fusing together everything from design to manufacturing and test in order to reduce the number and cost of silicon respins. The sheer density of modern chips, combined with advanced packaging techniques like 3D stacking and heterogeneous integration, has made iterative physical p... » read more

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