Stacked Die Changes

By Ed Sperling - 27 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 11 Apr, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Haya... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 31 Mar, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Uday Mitra, vice president and head of strategy and marketing for the Etch Bu... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 17 Mar, 2016 - Comments: 4

Challenges At Advanced Nodes

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

Challenges At Advanced Nodes

By Ed Sperling - 19 Aug, 2015 - Comments: 0

Challenges At Advanced Nodes

By Ed Sperling - 23 Jul, 2015 - Comments: 1

FD-SOI Vs. FinFETs

By Ed Sperling - 13 May, 2015 - Comments: 3

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 30 Apr, 2015 - Comments: 0

FD-SOI Vs. FinFETs

By Ed Sperling - 16 Apr, 2015 - Comments: 1

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Knowledge Centers
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category: Round Tables

category: IoT, Security & Automotive

Stacked Die Changes

Where Is Next-Gen Lithography?

Where Is Next-Gen Lithography?

Where Is Next-Gen Lithography?

Challenges At Advanced Nodes

Challenges At Advanced Nodes

Challenges At Advanced Nodes

FD-SOI Vs. FinFETs

FD-SOI Vs. FinFETs

FD-SOI Vs. FinFETs