Week In Review: Design, Low Power


Arteris IP will acquire the assets of Magillem Design Services, combining Arteris' NoC interconnect IP with Magillem's chip design and assembly environment. Magillem’s software products will continue to be offered separately from the Arteris interconnect IP offerings and the joined company will continue to execute on Magillem’s existing product and technology roadmaps. Substantially all Mag... » read more

System-Level Packaging Tradeoffs


Leading-edge applications such as artificial intelligence, machine learning, automotive, and 5G, all require high bandwidth, higher performance, lower power and lower latency. They also need to do this for the same or less money. The solution may be disaggregating the SoC onto multiple die in a package, bringing memory closer to processing elements and delivering faster turnaround time. But ... » read more

Blog Review: Sept. 30


Synopsys' Fred Bals takes a look open source projects that, while popular, go understaffed or underfunded, how that can lead to potential security vulnerabilities, and why users who rely on them should consider stepping up to contribute. In a video, Mentor's Colin Walls explains the basic concepts of multicore systems as it relates to embedded programming. Cadence's Paul McLellan ponders ... » read more

Tackling Functional Correctness, Safety, Trust And Security


We’re six months into the pandemic, and it looks like in-person conferences are becoming a distant memory and that virtual conferences are now becoming routine. It used to be that traveling to a conference (sometimes long distances) was the only way to be able to attend technical presentations and learn about the latest technologies and methodologies, and that was only if you received permiss... » read more

Deals That Change The Chip Industry


Nvidia's pending $40 billion acquisition of Arm is expected to have a big impact on the chip world, but it will take years before the effects of this deal are fully understood. More such deals are expected over the next couple of years due to several factors — there is a fresh supply of startups with innovative technology, interest rates are low, and market caps and stock prices of buyers ... » read more

The Next Wave Of Consolidation


End markets and technologies are changing, stock prices are up, and interest rates are down. Those are the necessary ingredients for acquisition binging. So why isn't much happening? The answer is that more industry consolidation is ahead, but it's all happening more slowly than the economics would suggest. Some of the reasons are obvious, others less so. The big delay is the COVID-19 pa... » read more

Week In Review: Design, Low Power


Tools & IP Arm added two new platforms to its product roadmap: the Neoverse V1, and the Neoverse N2, the second-generation N-series platform. The V1 platform supports Scalable Vector Extensions (SVE), provides 50% better single-threaded performance over N1, and targets high-performance cloud, HPC, and machine learning applications. The N2 provides 40% higher single-threaded performance com... » read more

Optimizing What Exactly?


You can't optimize something without understanding it. While we inherently understand what this means, we are often too busy implementing something to stop and think about it. Some people may not even be sure what it is that they should be optimizing and that makes it very difficult to know if you have been successful. This was a key message delivered by Professor David Patterson at the Embedde... » read more

Hyperscale And Edge Computing: The What, Where And How


We hear a lot about “edge computing” these days. We are approaching an era in which unfathomable amounts of data are created, which need to be transmitted, stored, processed and made sense of. As we are witnessing never-before-seen scaling in all those domains, the term “hyperscale” computing has been invented. But what about the edge? As it turns out, the definition seems to have chang... » read more

Innovative Strategies Are Improving Early Design Circuit Verification


Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, wh... » read more

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