category: System-Level Design

category: IoT, Security & Automotive

Domain-Specific Processors Enable More Than Moore
By Roddy Urquhart - 28 May, 2020 - Comments: 0

Last month was the 55th anniversary of Gordon Moore’s famous paper Cramming more components onto integrated circuits. He took a long-term view of the trends in integrated circuits being implemented using successively smaller feature sizes in silicon. Since that paper, integrated circuit developers have been relying on three of his predictions: The number of transistors per chip increas... » read more

Digital Immersion: The Next Step Towards The Future Of Mobile Devices And Connectivity
By Frank Schirrmeister - 28 May, 2020 - Comments: 0

In considering how far we’ve come with mobile devices just in the last two decades, it’s entertaining to think about the next ten years. When asking the new power users, Generation Z or the “digital natives,” a couple of key themes emerge, both for mobile devices, as well as for the networks they reside in. Some key advancements have been made this week with the announcement of Arm’s ... » read more

FPGA Equivalence Checking For A Nuclear Safety Controller
By Rob van Blommestein - 28 May, 2020 - Comments: 0

Every chip development team wants to find and fix all the bugs they possibly can in pre-silicon verification. Turning a chip to fix issues found in the bring-up lab incurs high costs and product delays; bugs found in the field are even more expensive to repair. But for some applications, including military/aerospace, implanted medical devices, and autonomous vehicles, the consequences of a faul... » read more

What’s So Important About Processor Extensibility?
By Brian Bailey - 28 May, 2020 - Comments: 1

While the ability to extend a processor is nothing new, market dynamics are forcing a growing percentage of the industry to consider it a necessary part of their product innovation. From small IoT functions to massive data centers and artificial intelligence, the need to create an optimized processing platform is often the only way to get more performance or lower power out of the silicon area ... » read more

Lower Resistance Protects Against Failure In IC Design
By Fady Fouad - 28 May, 2020 - Comments: 0

By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

FPGA Prototyping Complexity Rising
By Ann Mutschler - 28 May, 2020 - Comments: 0

Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

The Seven Steps Of Formal Signoff
By Iain Singleton - 28 May, 2020 - Comments: 0

“Signoff” may be the most exciting—and frightening—word in semiconductor development. After many months, or even years of team effort, committing a design to silicon fabrication is indeed an exciting and rewarding event. But, there’s often significant anxiety involved as well – if any missed issues result in having to “turn” the chip, the increased costs and time-to-market delay... » read more

What Will The Next-Gen Verification Flow Look Like?
By Ed Sperling - 28 May, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; and Nasr Ullah, senior director of performance architecture at SiFive. What follows are exc... » read more

Early Detection Of Power/Ground Shorts Speeds Time To Tapeout
By Mentor, a Siemens Business - 27 May, 2020 - Comments: 0

Early detection of power/ground shorts lets design teams fix errors during implementation, avoiding time-consuming design data merging and full-chip physical verification. The Calibre platform provides fast, automated power/ground checking using abstract LEF/DEF input, significantly reducing the time and resources needed to ensure these violations are removed prior to tapeout. To read more, ... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 May, 2020 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier ... » read more

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