category: System-Level Design

category: IoT, Security & Automotive

Configurable, Easy-To-Use, Packaged Reliability Checks
By Mentor, a Siemens Business - 18 Dec, 2019 - Comments: 0

Using a packaged checks flow lets designers quickly select, configure and run custom reliability checks and check combinations to help design companies achieve today’s demanding time-to-market schedules while ensuring product reliability. To read more, click here. » read more

Verdi Transaction Debug Platform: A Simplified Way To Debug IIP Designs And SoC
By Synopsys - 18 Dec, 2019 - Comments: 0

Authors: Abhishek Upadhyay, R&D Engineer, Synopsys, and Kanak Rajput, Application Engineer, Synopsys Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It’s not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the ... » read more

Kahn Process Network: Parallel Programming Without Races And Non-Determinism
By Silexica - 18 Dec, 2019 - Comments: 0

Modern personal computing devices feature multiple cores. This is not only true for desktops, laptops, tablets and smartphones, but also for small embedded devices like the Raspberry Pi. In order to exploit the computational power of those platforms, application programmers are forced to write their code in a parallel way. Most often, they use the threading approach. This means multiple parts o... » read more

Blog Review: Dec. 18
By Jesse Allen - 18 Dec, 2019 - Comments: 0

Lam Research's David Haynes finds that taking advances made at 300mm and applying them via upgrades to 200mm equipment is a cost appropriate strategy to quickly improve yield and add capacity. Synopsys' Taylor Armerding looks at which of this year's many data breaches hit corporate wallets the hardest and how the cost of privacy noncompliance is expected to rise with California's CCPA and st... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Dec, 2019 - Comments: 0

Rambus finalized its acquisition of the silicon IP, secure protocols and provisioning business from Verimatrix, formerly Inside Secure, for $45 million at closing, and up to an additional $20 million, subject to certain revenue targets in 2020. RISC-V SiFive unveiled two new product families. The SiFive Apex processor cores target mission-critical processors with Size, Weight, and Power (SW... » read more

Blog Review: Dec. 11
By Jesse Allen - 11 Dec, 2019 - Comments: 0

Arm's Urmish Thakker investigates ways to make recurrent neural networks run on resource constrained devices with limited cache and compute resources by reducing the number of RNN computations, without the need to retrain the original RNN model. Mentor's Brent Klingforth digs into the challenges of designing rigid-flex PCBs and how advanced capabilities in modern tools, like awareness of sta... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Dec, 2019 - Comments: 0

Cadence signed a deal to buy National Instruments’ AWR business unit for about $160 million in cash, a move that Cadence describes as a way to broaden its market into intelligent system design. AWR’s strength is high-frequency RF design automation tools, particularly in the millimeter wave and microwave spectrums, which are critical for radar and 5G. It also has technology for III-V materia... » read more

Distributed Design Implementation
By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Blog Review: Dec. 4
By Jesse Allen - 04 Dec, 2019 - Comments: 0

Arm's Rupal Gandhi digs into the Cell-Aware Test methodology to deterministically target the growing number of defects that occur within the cells, the process of CAT library generation, and compares the static and transition patterns generated. Cadence's Paul McLellan shares highlights from the recent WOSET event with a look at the big drivers for the current interest in open-source EDA too... » read more

Finding Hardware Trojans
By Ed Sperling - 03 Dec, 2019 - Comments: 0

John Hallman, product manager for trust and security at OneSpin Technologies, looks at how to identify hardware Trojans in a design, why IP from different vendors makes this more complicated, and how a digital twin can provide a reference point against which to measure if a design has been compromised. » read more

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