What’s Missing In 2.5D EDA Tools

By Brian Bailey - 28 Mar, 2024 - Comments: 0

Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

Staying Within The Margins

By Barry Pangrle - 28 Mar, 2024 - Comments: 0

Last March I wrote an article called Squeezing the Margins that’s about a design that used an adaptive clocking scheme to keep the performance of a system high while simultaneously keeping the temperature below a specified maximum. Last August we looked at Managing Voltage Variation and how an adaptive clocking scheme could be used to manage dynamic voltage drop to maximize system performance... » read more

Interconnects Essential To Heterogeneous Integration

By Karen Heyman - 28 Mar, 2024 - Comments: 0

Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?

By Ann Mutschler and Adam Kovac - 28 Mar, 2024 - Comments: 0

Experts at the table: Finding and eliminating bugs at the source can be painstaking work, but it can prevent bigger problems later in the design flow, when they are more difficult and expensive to fix. Semiconductor Engineering sat down to discuss these issues with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software... » read more

Rapid Timing Constraints Signoff With Automated Constraint Management

By Rimpy Chugh - 28 Mar, 2024 - Comments: 0

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a tool must be tied closely into the logic synthesis process to make it more likely that the generated gate-level netlist will meet the desired timing. Power, performance, and area (PPA) goals can o... » read more

A New Strategy For Successful Block/Chip Design-Stage Verification

By David Abercrombie - 28 Mar, 2024 - Comments: 0

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening time-to-market constraints and the finite resources at their disposal, while ensuring the quality of their designs remains uncompromised. Traditionally, IC design flows have been depicted as a linear ... » read more

Data Acquisition Software: The Brains Behind The Hardware

By Bernard Ang - 28 Mar, 2024 - Comments: 0

We have previously talked about how data acquisition systems streamline the testing of various test scenarios. However, the data acquisition (DAQ) hardware is just one-half of the equation. To make the hardware useful for various test scenarios, you need suitable data acquisition software and firmware that can take advantage of that powerful hardware and bridge the gap between your needs and... » read more

Navigating Design Challenges

By Siemens EDA - 28 Mar, 2024 - Comments: 0

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop v... » read more

Jumpstarting The Automotive Chiplet Ecosystem

By Steve Brown - 28 Mar, 2024 - Comments: 0

The automotive industry stands on the cusp of a technological renaissance, ushering in an era where vehicles aren't just tools of transportation, but interconnected nodes within a vast network of software-defined mobility. Central to this transformation is the concept of chiplets—miniaturized, modular components that can be mixed, matched, and scaled to create powerful, application-specific i... » read more

Everything You Need to Know About Wi-Fi 7

By Keysight - 27 Mar, 2024 - Comments: 0

The IEEE 802.11be standard introduces several new features for improving WLAN efficiency, capacity, and coverage. Features such as multi-link operation (MLO) and multiple resource units (multi-RUs) increase the number of configurations and test scenarios to validate a device thoroughly. In addition to physical-layer testing, test engineers must emulate signaling to verify interactions between a... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.