Multiple Challenges Emerge With Physical AI System Design


Physical AI holds the promise of making everything from robots to a slew of mobile edge devices much more interactive and useful, but it will significantly alter how systems are designed, verified, and monitored. Physical AI systems need to work both independently and together. They need the ability to make decisions quickly and locally, typically using much less power than other types of AI... » read more

Blog Review: Oct. 22


Cadence's Sandip Sadadiya shows what's new in the AMBA AXI Issue L protocol update, which introduces a new credit-based transport mechanism that replaces the traditional VALID/READY handshake, along with improved flow control mechanisms. Siemens' Farhad Ahmed highlights the growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way and intro... » read more

Multi-Die Verification


Chiplets offer unprecedented flexibility in high-performance designs, but they also add new challenges on the verification side. Changing out a chiplet, or adding a new one, can mean having to re-verify an entire multi-die system, a problem that becomes even more complicated if those chiplets are developed by different vendors. Paul Graykowski, director of product marketing at Cadence Design Sy... » read more

The Critical Role Of Virtualization In Automotive Software Development For Software-Defined Vehicles


By Chahinez Hamlaoui, Robert Fey, and David Howarth The automotive industry is undergoing a profound transformation. Vehicles are no longer just mechanical machines, they are becoming sophisticated, software-defined platforms packed with electronics and intelligence. As the number of electronic control units (ECUs) in modern vehicles climbs (with some cars now containing up to 150 ECUs), the... » read more

Blog Review: Oct. 8


Siemens' Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates. Cadence's Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI ... » read more

How 3D-IC Will Change Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

Silicon IP Continues Steady Growth Path


EDA and silicon IP revenue increased 8.6% to $5.089 billion in Q2 2025, up from $4.6855 billion in Q2 2024, according to the ESD Alliance. Total EDA revenue growth was assisted by impressive results in the CAE category, the largest tool sector, which showed 17.2% growth over Q2 2024. “It was another good quarter overall," said Walden C. Rhines, executive sponsor of the SEMI Electronic Desi... » read more

Chip Industry Startup Funding: Q3 2025


The third quarter of 2025 was dominated by massive rounds for companies developing AI chips and quantum computers. Over $2.5 billion went to AI, with wafer-scale chip maker Cerebras leading the pack with a $1.1 billion raise. While several edge AI companies received backing, the quarter saw a marked shift towards solutions for the data center as firms seek to reduce the cost and power consumpti... » read more

Why The Next Breakthrough In Chips Depends On Rethinking Design Workflows


At this year’s DAC Chips to Systems Conference (DAC 2025), Keysight and its partners showcased how engineers are rethinking design workflows from chips to complete systems. The Partner Theater, hosted by Keysight brought together innovators from across the semiconductor ecosystem – each tackling one of today’s most pressing challenges: how to manage exploding volumes of design data and le... » read more

Blog Review: Oct. 1


Synopsys' Chun-Soo Kim and Hoseong Kim suggest making the entire design flow local layout effect-aware to identify and address issues early and ultimately improve PPA by avoiding overly pessimistic designs. Siemens' Kirk Fabbri explores the power distribution network, focusing on power plane capacitance and how it varies with the dynamic switching characteristics of the load and dielectric c... » read more

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