First Forays Into True 3D-IC Designs


Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager... » read more

Benefits And Challenges Of Using Chiplets


The move to chiplets opens the door to more features than can be packed into a reticle-sized SoC. That potentially means more processing power, simpler designs, and higher yields. But it's not as simple as swapping LEGO blocks into a chassis. Ashley Stevens, director of product management and marketing at Arteris, talks with Semiconductor Engineering about the challenges of using coherent versu... » read more

Speeding Time To Market With A Future-Proof Fabric


This whitepaper covers how Tenstorrent is elevating their AI fabric to new heights of performance, efficiency, and productivity through a collaboration with Baya Systems. Tenstorrent’s in-house fabric has set a new standard for efficiency and performance in AI compute in their current generation products and is proactively addressing the needs of the next generation. By combining Tenstorrent�... » read more

The Future Of Verification


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Blog Review: Sept. 24


Siemens' Harry Foster warns of a big drop in first-time silicon success as more system companies tackle developing their own chip without the accumulated knowledge around flows, sign-off criteria, and coverage closure in a landscape where even small oversights in methodology can lead to multimillion-dollar respins. Synopsys' Godwin Maben warns that skyrocketing power consumption is a critica... » read more

Beyond the Bottleneck: AI Cluster Networking Report 2025


Artificial intelligence (AI) is the engine of next-generation innovation. However, increasing complexity means increased demand on data center networks. As AI grows into a central component of enterprise strategies, organizations must carefully consider how they design, test, and scale their infrastructure. This report, based on a global survey conducted by Heavy Reading in collaboration with K... » read more

New Demands For IP Reuse


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight;... » read more

Blog Review: Sept. 17


Siemens' John McMillan explores the fundamentals of IC package thermal resistance, modeling strategies, and why die-level thermal analysis in 3D-ICs is increasingly essential for ensuring device reliability. Cadence's Jasmine Makhija provides an overview of the TEE Device Interface Security Protocol (TDISP), which helps safeguard PCIe devices within Trusted Execution Environments by providin... » read more

Inside Chips Podcast: Data Movement In The AI Age


AI is all about data movement — lots of it. The key is to move data as little as possible, and when it is moved, to do it efficiently, securely, and blindingly fast. Semiconductor Engineering talks with Arteris CEO Charlie Janac in this one-on-one discussion about the impact of AI on networks on chip and what will change going forward. To listen to the podcast, click here. » read more

Blog Review: Sept. 10


Cadence's Satish Kumar C explains Port-Based Routing, a feature in in CXL 3.0 and 3.1 that changes how CXL switches operate within a CXL fabric to enable the creation of much larger, more flexible, and more efficient topologies. Siemens' Bill Hargin demystifies copper foil thickness and weight measurements and why being precise has an impact on signal integrity and crosstalk simulations.... » read more

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