category: System-Level Design

category: IoT, Security & Automotive

AI Drives Re-Engineering Of Nearly Everything In Chips
By Ed Sperling - 24 Apr, 2025 - Comments: 0

AI's ability to mine patterns across massive quantities of data is causing fundamental changes in how chips are used, how they are designed, and how they are packaged and built. These shifts are especially apparent in high-performance AI architectures being used inside of large data centers, where chiplets are being deployed to process, move, and store massive amounts of data. But they also ... » read more

AI-Driven Verification Regression Management
By Paul Carzola - 24 Apr, 2025 - Comments: 0

By Paul Carzola and Taruna Reddy Coping with the endless growth in chip size and complexity requires innovative electronic design automation (EDA) solutions at every stage of the development process. Better algorithms, increased parallelism, higher levels of abstraction, execution on graphics processing units (GPUs), and use of AI and machine learning (ML) all contribute to these solutions. ... » read more

Reap Rewards With Shift-Left Pattern Matching For Custom And AMS Designs
By John Muirhead - 24 Apr, 2025 - Comments: 0

To keep up with the growing complexities of IC design, major semiconductor companies are adopting shift-left strategies. For verification, this means pulling much of the work into the physical design stage. By moving critical checks earlier in the design cycle, you can identify and resolve issues before they escalate, streamlining the overall development process. The Calibre tools have been ... » read more

New Ways To Improve EDA Productivity
By Ann Mutschler - 24 Apr, 2025 - Comments: 0

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling to keep pace with exponential increases in chip complexity in tight time-to-market windows and with constrained engineering talent pipelines. In the past, progress often was as straightforward as improving algorithms or parallelizing computations in a linear flow. But w... » read more

NOP Flit Payload: A Dedicated Debug Channel
By Geeta Arora - 24 Apr, 2025 - Comments: 0

Modern PCIe systems are complex, with high-speed data transfer and intricate protocols. Traditional debug methods often struggle to provide the necessary granularity and real-time visibility into link behavior. Transient issues, timing-sensitive errors, and protocol interactions can be difficult to pinpoint with conventional methodology. NOP Flit addresses this challenge. PCIe Gen 6 introduc... » read more

Analog Creates Ripples in Digital Verification
By Brian Bailey - 24 Apr, 2025 - Comments: 0

We live in an analog world, but analog has been minimized whenever possible. At some point digital and analog must come together in every electronic device, and that has long been an area where errors creep in. The Wilson Research Group and Siemens EDA functional verification study has long shown that analog and mixed signal are two of the highest causes of flaws that result in chip respins.... » read more

What Is Electronic Design Automation And Why Do You Need It?
By Roberto Piacentini Filho - 24 Apr, 2025 - Comments: 0

As data speeds push into the multi-gigabit range and requirements on digital systems grow more complex, cutting down the time-to-market while also ensuring error-free reliable designs seems impossible. Traditional design tools and practices can result in failed prototypes, costly respins, delayed time-to-market, missed market opportunities, and subpar performance. This is why advanced EDA to... » read more

Multi-Die Design Start Guide
By Synopsys - 23 Apr, 2025 - Comments: 0

If you are exploring a multi-die project and need guidelines on getting started, this white paper is for you. Any engineer on a semiconductor design project has read many articles about the power, performance, and area (PPA), functional scalability, and time-to-market advantages of multi-die designs using 2.5D and 3D technologies. The advantages are the main reason the adoption of multi-die des... » read more

Accelerating SI/PI Signoff: A Shift-Left Approach to PCB Design
By Cadence - 23 Apr, 2025 - Comments: 0

In high-speed PCB design, late-stage signal integrity (SI) and power integrity (PI) issues can lead to costly redesigns and delays. This white paper explores how in-design analysis helps engineers catch and fix SI/PI challenges early, saving time, reducing risks, and ensuring first-pass success. What You’ll Learn: The Shift-Left Advantage – How early SI/PI analysis minimizes late-s... » read more

Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design
By Arteris - 23 Apr, 2025 - Comments: 0

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. Business Challenge • Develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. Design Challenges • Ensure different portions ... » read more

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