category: System-Level Design

category: IoT, Security & Automotive

Lines Blurring Between Supercomputing And HPC
By Ann Mutschler - 27 Feb, 2025 - Comments: 1

Supercomputers and high-performance computers are becoming increasingly difficult to differentiate due to the proliferation of AI, which is driving huge performance increases in commercial and scientific applications and raising similar challenges for both. While the goals of supercomputing and high-performance computing (HPC) have always been similar — blazing fast processing — the mark... » read more

Key Challenges In Scaling AI Clusters
By Emily Yan - 27 Feb, 2025 - Comments: 0

AI is evolving at an unprecedented pace, driving an urgent need for more powerful and efficient data centers. In response, nations and companies are ramping up investments into AI infrastructure. According to Forbes, AI spending from the Big Tech sector will exceed $250 billion in 2025, with the bulk going towards infrastructure. By 2029, global investments in AI infrastructure, including dat... » read more

Bold Prediction: 50% Of New HPC Chip Designs Will Be Multi-Die In 2025
By Shekhar Kapoor - 27 Feb, 2025 - Comments: 0

Monolithic chips have been the workhorses behind decades of technological advancement. But just as the industrial revolution saw workhorses replaced with more efficient and powerful machinery, the semiconductor industry is on the cusp of a similar revolution. Multi-die and chiplet-based designs — which integrate multiple specialized dies in a single package or stack integrated circuits ver... » read more

Top 5 Reasons Engineers Need A Smart NoC
By Rick Bye - 27 Feb, 2025 - Comments: 0

As system-on-chip (SoC) designs grow more complex, IP interconnect engineers struggle with achieving optimal scalability, performance, and power efficiency. The increasing number of IP blocks, often ranging from 50 to more than 500, introduces significant interconnect congestion, timing closure issues, and power dissipation challenges. Additionally, many network-on-chip (NoC) design tasks are s... » read more

Multi-Die Design Complicates Data Management
By Adam Kovac - 27 Feb, 2025 - Comments: 0

The continued unbundling of SoCs into multi-die packages is increasing the complexity of those designs and the amount of design data that needs to be managed, stored, sorted, and analyzed. Simulations and test runs are generating increasing amounts of information. That raises questions about which data needs to be saved and for how long. During the design process, engineers now must wrestle ... » read more

A Novel Approach For Hardware-Software Co-Verification
By Siemens EDA - 26 Feb, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

Pre-Silicon Verification Of Die-to-Die IP With Novel ESD Protection
By Synopsys - 26 Feb, 2025 - Comments: 0

All major foundries have adopted the programmable electrical rule checker (PERC) as the pre-silicon electrostatic discharge (ESD) signoff tool for IP and chip designs. This concept of rule checking works fine for most IP types, but for die-to-die IP, used in 3DIC designs, the PERC approach may not be appropriate. Die-to-die interface IP includes extremely large numbers of I/Os, trending towards... » read more

Boost SoC Efficiency And Speed With FlexGen Smart NoC IP Automation
By Arteris - 26 Feb, 2025 - Comments: 0

Today’s high-end SoCs contain many heterogeneous processing elements to address the needs of HPC and AI applications. These include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Tensor Processing Units (TPUs), and other hardware accelerators. Furthermore, IPs may contain clusters of these processor cores, and SoC subsystems may include arra... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies With Functional Partitioning Of Many-Core RISC-V SoC
By Cadence - 26 Feb, 2025 - Comments: 0

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. This white paper analyzes the impact of mat... » read more

Cracking The Memory Wall
By Ed Sperling - 26 Feb, 2025 - Comments: 0

Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

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