category: System-Level Design

category: IoT, Security & Automotive

Digital Twins For Design And Verification Workflows
By Brian Bailey - 27 Mar, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to a single tool or small flows provided by a single company. What is required is a digital twin of the development process itself, on which AI can operate. Semiconductor Engineering sat down with a panel of experts, including Johannes Stahl, senior d... » read more

Virtualizer Native Execution Accelerates Software Defined Product Development for Arm Solutions
By Synopsys - 26 Mar, 2025 - Comments: 0

This whitepaper highlights advancements in virtual prototyping with near native execution performance. The adoption of Arm processor architecture in automotive and data centers is driven by software complexity and ECU consolidation. This shift elevates virtualization performance requirements, supported by Arm's mature software ecosystem. Key Takeaways: Adoption of and convergence of bot... » read more

Dynamic Characterization Of A Power Semiconductor Bare Chip
By Keysight - 26 Mar, 2025 - Comments: 0

Power semiconductor devices are used in a variety of forms, such as being packaged in Surface Mount Devices (SMDs) or power modules, and they find broad applications. Power semiconductor bare chips are loaded into these packages. It is desirable to characterize the bare chip before placing it in a package or a power module to expedite development. However, the small size, fragile structure, and... » read more

Accelerate And Derisk RISC-V- Based SoC Designs
By Arteris - 26 Mar, 2025 - Comments: 0

How to accelerate and derisk RISC-V-based SoC designs using silicon-proven network-on-chip IP and SoC integration automation software. This technology seamlessly connects any IP from multiple vendors and shortens design cycles and time to revenue. Maximize overall efficiency for the best product design, leveraging the best NoC IP and expert support. Read more here. » read more

The Evolving Role Of AI In Verification
By Ann Mutschler - 26 Mar, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure the functional correctness of devices has increased exponentially as chips have gotten more complex and evolved into SoC, 3D-ICs, multi-die chiplets and beyond. Semiconductor Engineering sat down with a panel of experts, which included Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group dir... » read more

Blog Review: Mar. 26
By Jesse Allen - 26 Mar, 2025 - Comments: 0

Siemens' Bianca Ward argues that sustainability must be considered starting from the design phase to reduce the energy consumption of ICs as well as the production processes used to manufacture them. Synopsys' Adrien Tozzoli looks at how physical optics simulation can be improved by using beam synthesis propagation, a method that decomposes the optical field into a collection of beamlets to ... » read more

Allegro X AI for Generative System Design
By Cadence - 26 Mar, 2025 - Comments: 0

PCB design is the act of realizing a schematic into a physical form. Currently, human designers use electronic design automation (EDA) software to combine component placement and routing to realize the electrical connectivity on a manufacturable PCB. Computer-aided design (CAD) tools have been used in the design flow since the 1970s and are now an essential part of the designer’s toolkit. Som... » read more

Blog Review: Mar. 19
By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

Optimizing Data Movement In SoCs And Advanced Packages
By Ed Sperling - 18 Mar, 2025 - Comments: 0

The amount of data that needs to move around a chip is growing exponentially, driven by the rollout of AI and more sensors everywhere. There may be hundreds of IP blocks, more compute elements, and many more wires to contend with. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the demand for low-latency on-chip communication in increasingly complex ... » read more

Blog Review: Mar. 12
By Jesse Allen - 12 Mar, 2025 - Comments: 0

Cadence's P. Saisrinivas explains the relationship between drive strength and cell delay and why it is key to choose the appropriate drive strength to meet timing constraints while minimizing power and area. Siemens' Daniel Berger and Dirk Hartmann tackle the readout problem of accurately measuring the state of a quantum system after it has undergone a quantum computation, which becomes incr... » read more

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