category: Architectures

category: IoT, Security & Automotive

Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware
By Technical Paper Link - 10 Mar, 2022 - Comments: 0

Abstract "Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bo... » read more

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more

Hybrid architecture based on two-dimensional memristor crossbar array and CMOS integrated circuit for edge computing
By Technical Paper Link - 27 Jan, 2022 - Comments: 0

Abstract "The fabrication of integrated circuits (ICs) employing two-dimensional (2D) materials is a major goal of semiconductor industry for the next decade, as it may allow the extension of the Moore’s law, aids in in-memory computing and enables the fabrication of advanced devices beyond conventional complementary metal-oxide-semiconductor (CMOS) technology. However, most circuital demons... » read more

A crossbar array of magnetoresistive memory devices for in-memory computing
By Technical Paper Link - 14 Jan, 2022 - Comments: 0

Samsung has demonstrated the world’s first in-memory computing technology based on MRAM. Samsung has a paper on the subject in Nature. This paper showcases Samsung’s effort to merge memory and system semiconductors for next-generation artificial intelligence (AI) chips. Abstract "Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-po... » read more

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance ... » read more

Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "Adaptation in time-triggered systems can be motivated by energy efficiency, fault recovery, and changing environmental conditions. Adaptation in time-triggered systems is achieved by preserving temporal predictability through metascheduling techniques. Nevertheless, utilising existing metascheduling schemes for time-triggered network-on-chip architectures poses design time computatio... » read more

Design of strongly nonlinear graphene nanoelectromechanical systems in quantum regime
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

ABSTRACT "We report on the analysis and design of atomically thin graphene resonant nanoelectromechanical systems (NEMS) that can be engineered to exhibit anharmonicity in the quantum regime. Analysis of graphene two-dimensional (2D) NEMS resonators suggests that with device lateral size scaled down to ∼10–30 nm, restoring force due to the third-order (Duffing) stiffness in graphene NE... » read more

An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks
By Technical Paper Link - 20 Dec, 2021 - Comments: 0

Abstract:  "The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without clock architecture, with co-lo... » read more

Factoring 2048-bit RSA Integers in 177 Days with 13 436 Qubits and a Multimode Memory
By Technical Paper Link - 18 Nov, 2021 - Comments: 0

Abstract: "We analyze the performance of a quantum computer architecture combining a small processor and a storage unit. By focusing on integer factorization, we show a reduction by several orders of magnitude of the number of processing qubits compared with a standard architecture using a planar grid of qubits with nearest-neighbor connectivity. This is achieved by taking advantage of a tem... » read more

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract: "Characterization of real DRAM devices has enabled findings in DRAM device properties, which has led to proposals that significantly improve overall system performance by reducing DRAM access latency and power consumption. In addition to improving system performance, a deeper understanding of DRAM technology via characterization can also improve device reliability and security. The... » read more

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