category: Architectures

category: IoT, Security & Automotive

Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "Adaptation in time-triggered systems can be motivated by energy efficiency, fault recovery, and changing environmental conditions. Adaptation in time-triggered systems is achieved by preserving temporal predictability through metascheduling techniques. Nevertheless, utilising existing metascheduling schemes for time-triggered network-on-chip architectures poses design time computatio... » read more

Design of strongly nonlinear graphene nanoelectromechanical systems in quantum regime
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

ABSTRACT "We report on the analysis and design of atomically thin graphene resonant nanoelectromechanical systems (NEMS) that can be engineered to exhibit anharmonicity in the quantum regime. Analysis of graphene two-dimensional (2D) NEMS resonators suggests that with device lateral size scaled down to ∼10–30 nm, restoring force due to the third-order (Duffing) stiffness in graphene NE... » read more

An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks
By Technical Paper Link - 20 Dec, 2021 - Comments: 0

Abstract:  "The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without clock architecture, with co-lo... » read more

Factoring 2048-bit RSA Integers in 177 Days with 13 436 Qubits and a Multimode Memory
By Technical Paper Link - 18 Nov, 2021 - Comments: 0

Abstract: "We analyze the performance of a quantum computer architecture combining a small processor and a storage unit. By focusing on integer factorization, we show a reduction by several orders of magnitude of the number of processing qubits compared with a standard architecture using a planar grid of qubits with nearest-neighbor connectivity. This is achieved by taking advantage of a tem... » read more

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract: "Characterization of real DRAM devices has enabled findings in DRAM device properties, which has led to proposals that significantly improve overall system performance by reducing DRAM access latency and power consumption. In addition to improving system performance, a deeper understanding of DRAM technology via characterization can also improve device reliability and security. The... » read more

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract "RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability worsens as DRAM cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern DRAM chips, including chips previously marketed as RowHammer-safe, are even more vulnerable to RowHammer than... » read more

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment
By Technical Paper Link - 09 Nov, 2021 - Comments: 0

Summary "To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a malicious operating system. TEEs are usually built by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these... » read more

A Compact Model For Scalable MTJ Simulation
By Technical Paper Link - 24 Aug, 2021 - Comments: 0

Read the full technical paper. Published June 9, 2021. Abstract This paper presents a physics-based modeling framework for the analysis and transient simulation of circuits containing Spin-Transfer Torque (STT) Magnetic Tunnel Junction (MTJ) devices. The framework provides the tools to analyze the stochastic behavior of MTJs and to generate Verilog-A compact models for their simulation in lar... » read more

2D materials–based homogeneous transistor-memory architecture for neuromorphic hardware
By Technical Paper Link - 21 Aug, 2021 - Comments: 0

Abstract "In neuromorphic hardware, peripheral circuits and memories based on heterogeneous devices are generally physically separated. Thus exploring homogeneous devices for these components is an important issue for improving module integration and resistance matching. Inspired by ferroelectric proximity effect on two-dimensional materials, we present a tungsten diselenide-on-LiNbO3 cascaded... » read more

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology
By Technical Paper Link - 19 Aug, 2021 - Comments: 0

Abstract: "Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy