category: Materials

category: IoT, Security & Automotive

Improving the Electrical Performance and Low-Frequency Noise Properties of p-Type TFET
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET" was published by researchers at Chungnam National University and Korea Polytechnic College. "This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silic... » read more

Novel Multi-Independent Gate-Controlled FinFET Technology
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)" was published by researchers at Changzhou University. Abstract: "This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific device... » read more

Red MicroLEDs Three Orders of Magnitude Smaller in Surface Area
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "N-polar InGaN/GaN nanowires: overcoming the efficiency cliff of red-emitting micro-LEDs" was published by researchers at University of Michigan. The researchers created "red-microLEDs that are nearly three orders of magnitude smaller in surface area than previously reported devices while exhibiting external quantum efficiency of ~1.2%," according to the University o... » read more

Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)
By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A technical paper titled "Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits" was published by researchers at Imec. "The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full waf... » read more

Bottoms Up: Arranging Nanoscale Particles On A Silicon Chip (Or Other Materials) Without Damage
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new research paper titled "Nanoparticle contact printing with interfacial engineering for deterministic integration into functional structures" was just published by researchers at MIT. “This approach allows you, through engineering of forces, to place the nanoparticles, despite their very small size, in deterministic arrangements with single-particle resolution and on diverse surfaces, ... » read more

3D Racetrack Memory Device (Max Planck)
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new technical paper titled "Three-dimensional racetrack memory devices designed from freestanding magnetic heterostructures" was published by researchers at Max Planck Institute of Microstructure Physics in Halle, Germany. "Magnetic racetrack memory encodes data in a series of magnetic domain walls that are moved by current pulses along magnetic nanowires. To date, most studies have focuse... » read more

On-chip 2D/3D Photonics Integration Solution Using Deposited Polycrystalline Silicon for Optical Interconnects Applications
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Polycrystalline silicon PhC cavities for CMOS on-chip integration" was published by researchers at Tyndall National Institute, Munster Technological University, and Université Grenoble Alpes, CEA, LETI. "In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited polycrystalli... » read more

Wafer Scale Tool To Transfer Graphene
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Assessment of wafer-level transfer techniques of graphene with respect to semiconductor industry requirements" was published by researchers at RWTH Aachen University, AMO GmbH, Infineon Technologies, Protemics GmbH, and Advantest Europe. Abstract (partial): "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based elect... » read more

Hardware Platform Based on 2D Memtransistors
By Technical Paper Link - 15 Oct, 2022 - Comments: 0

A new technical paper titled "Hardware implementation of Bayesian network based on two-dimensional memtransistors" from researchers at Penn State University. "In this work, we demonstrate hardware implementation of a BN [Bayesian networks] using a monolithic memtransistor technology based on two-dimensional (2D) semiconductors such as monolayer MoS2. First, we experimentally demonstrate a lo... » read more

Transistor-Free Compute-In-Memory Architecture
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes" was recently published by researchers at University of Pennsylvania, Sandia National Labs, and Brookhaven National Lab. The compute-in-memory design is different as it is completely transistor-free. “Even when used in a compute-in-memory architecture, transistors compromise the access... » read more

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