category: Packaging

category: IoT, Security & Automotive

Evaluation of the Thermomechanical Reliability of Electronic Packages Using Virtual Prototyping
By Technical Paper Link - 18 Mar, 2023 - Comments: 0

A new technical paper titled "Design Optimization by Virtual Prototyping Using Numerical Simulation to Ensure Thermomechanical Reliability in the Assembly and Interconnection of Electronic Assemblies" was published by Fraunhofer ENAS. Abstract "A methodology is presented that allows the evaluation of the thermomechanical reliability of electronic packages using “virtual prototyping.” He... » read more

Chiplet Placer with Thermal Consideration for 2.5D ICs
By Technical Paper Link - 27 Feb, 2023 - Comments: 0

A new technical paper titled "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration" was published by researchers at National Yang Ming Chiao Tung University (Taiwan). Abstract "This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

ILP-Based Router for Wire-Bonding FBGA Packaging Design
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "ILP-Based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design" was written by researchers at National Taiwan University of Science and Technology. "In this paper, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-depende... » read more

Modeling and Thermal Analysis of 3DIC
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design
By Technical Paper Link - 14 Dec, 2022 - Comments: 0

A new technical paper titled "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems" was published by researchers at Hongik University, Seoul, South Korea. "An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digi... » read more

An Arrangement of Chiplets That Outperforms A Grid Arrangement (ETH Zurich / U. of Bologna)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A research paper titled "HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement" was published by researchers at ETH Zurich and University of Bologna. Abstract: "2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects ... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

Cost Characteristics of the 2.5D Chiplet-Based SiP System
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies" was published by researchers at UCSB, University of California, Santa Barbara. Abstract: "The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to ... » read more

Securing Heterogeneous Integration at the Chiplet, Interposer, and System-In-Package Levels (FICS-University of Florida)
By Technical Paper Link - 04 Aug, 2022 - Comments: 0

A new research paper titled "ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance" was published by researchers at the Florida Institute for Cybersecurity (FICS) Research, University of Florida. Abstract "The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Pa... » read more

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