category: Top Stories

category: IoT, Security & Automotive

Regaining The Edge In U.S. Chip Manufacturing
By Mark LaPedus & Ann Steffora Mutschler - 26 Oct, 2020 - Comments: 16

The United States is developing new strategies to prevent it from falling further behind Korea, Taiwan, and perhaps even China in semiconductor manufacturing, as trade tensions and national security concerns continue to grow. For years, the U.S. has been a leader in the development of new chip products like GPUs and microprocessors. But from a chip manufacturing standpoint, the U.S. is losin... » read more

Defect Challenges Grow For IC Packaging
By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Several vendors are ramping up new inspection equipment based on infrared, optical, and X-ray technologies in an effort to reduce defects in current and future IC packages. While all of these technologies are necessary, they also are complementary. No one tool can meet all defect inspection requirements. As a result, packaging vendors may need to buy more and different tools. For years, p... » read more

Much Smarter Manufacturing
By Ed Sperling - 22 Oct, 2020 - Comments: 0

Smart manufacturing is undergoing some fundamental changes as more sensors are integrated across fabs to generate more usable data, and as AI/ML systems are deployed to sift through that data and identify patterns and anomalies more quickly. The concept of smart manufacturing — also referred to as Industrie 4.0 in Europe, for the fourth industrial revolution — emerged from the World Econ... » read more

Mask/Lithography Issues For Mature Nodes
By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. ... » read more

Making Chips To Last Their Expected Lifetimes
By Ed Sperling - 21 Oct, 2020 - Comments: 2

Chips are supposed to last their lifetime, but that expectation varies greatly depending upon the end market, whether the device is used for safety- or mission-critical applications, and even whether it can be easily replaced or remotely fixed. It also depends on how those chips are used, whether they are an essential part of a complex system, and whether the cost of continual monitoring and... » read more

Increase In Analog Problems
By Brian Bailey - 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

Slower Metal Bogs Down SoC Performance
By Bryon Moyer - 15 Oct, 2020 - Comments: 0

Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

Searching For Power Bugs
By Brian Bailey - 15 Oct, 2020 - Comments: 0

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Confusion Grows Over Packaging And Scaling
By Ann Mutschler - 15 Oct, 2020 - Comments: 0

The push toward both multi-chip packaging and continued scaling of digital logic is creating confusion about how to classify designs, what design tools work best, and how to best improve productivity and meet design objectives. While the goals of design teams remains the same — better performance, lower power, lower cost — the choices often involve tradeoffs between design budgets and ho... » read more

Why Data Format Slows Chip Manufacturing Progress
By Susan Rambo - 14 Oct, 2020 - Comments: 0

The Standard Test Data Format (STDF), a workhorse data format used to pull test results data from automated test equipment, is running out of steam after 35 years. It is unable to keep up with the explosive increase in data generated by more sensors in various semiconductor manufacturing processes. First developed in 1985 by Teradyne, STDF is a binary format that is translated into ASCII or ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy