SRAM In AI: The Future Of Memory


Experts at the Table — Part 1: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part two of this conversation can be found here and part three is here. [L-R]: ... » read more

Startup Funding: October 2023


Investors are betting heavily on data center technology, with October funding going to companies developing data processing units (DPUs) to accelerate a variety of tasks, a near-memory distributed dataflow architecture for AI, and liquid cooling technology. Much of this is linked to the build-out of the edge, closer to the source of the data than the cloud but not as compute-intensive. Other ... » read more

New Insights Into IC Process Defectivity


Finding critical defects in manufacturing is becoming more difficult due to tighter design margins, new processes, and shorter process windows. Process marginality and parametric outliers used to be problematic at each new node, but now they are persistent problems at several nodes and in advanced packaging, where there may be a mix of different technologies. In addition, there are more proc... » read more

DRAM Test And Inspection Just Gets Tougher


DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

Rebalancing Test And Yield In IC Manufacturing


Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Bug, Flaw, Or Cyberattack?


The lines between counterfeiting, security, and design flaws are becoming increasingly difficult to determine in advanced packages and process nodes, where the number of possible causes of unusual behavior grow exponentially with the complexity of a device. Strange behavior may be due to a counterfeit part, including one that contains a trojan. Or it may be the result of a cyberattack. It al... » read more

For SDVs, Software Is The Biggest Challenge


Software-defined vehicles (SDVs) involve far more than just OTA applications enabling software upgrades over the air. Software that will manage hundreds of ECUs and other functions within the vehicle is expected to grow beyond hundreds of millions of lines of code, possibly making SDV software development the number one challenge in automotive design. The benefits of SDVs, such as easy updat... » read more

Data Leakage In Heterogeneous Systems


Semiconductor Engineering sat down with Paul Chou, senior director of security architecture at NVIDIA, to discuss data leakage in heterogeneous designs. What follows are excerpts of that one-on-one interview, which was held in front of a live audience at the Hardwear.io conference. SE: We think about hardware in terms of a chip, but increasingly there is data moving through different systems... » read more

Isolating Critical Data In Failure Analysis


Experts at the Table: Semiconductor Engineering sat down to discuss traceability and the lack of data needed to perform root cause analysis with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran Hakim, ASIC reliability engineer at Teradyne... » read more

What Will That Chip Cost?


In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

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