Startup Funding: Q2 2025


Investors were drawn to a wide range of innovative approaches in Q2 2025, backing startups developing superconducting logic, chips for an emerging number format, big data processors, and novel power semi architectures. At the same time, photonics continues to draw investment dollars due to its ability to move data faster and with less energy at both the chip-to-chip and data center levels. T... » read more

Easing The Stress For Package-Level Burn-In


Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and multi-chiplet packages become more common, and concerns about aging circuitry heighten, shifting stress testing to the wafer level looks increasingly attractive from a quality, throughput, and cost standp... » read more

How Advanced Packaging Is Reshaping Inspection


As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

Detecting Slips, Scratches, Cracks In Wafers And Dies Becoming Harder


Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection tools’ resolution and throughput at foundries and OSATs. However, defects that manifest as slips, scratches, and micro-cracks continue to bedevil the prevalent optical inspection methods. These defects can range in size from nanometers to millimeters, some of which are... » read more

AI Pushes High-End Mobile From SoCs To Multi-Die


Advanced packaging is becoming a key differentiator for the high end of the mobile phone market, enabling higher performance, more flexibility, and faster time to market than systems on chip. Monolithic SoCs likely will remain the technology of choice for low-end and midrange mobile devices because of their form factor, proven record, and lower cost. But multi-die assemblies provide more fle... » read more

AI: A New Tool For Hackers, And For Preventing Attacks


Semiconductor Engineering sat down to discuss hardware security challenges, including new threat models from AI-based attacks, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit Arora, seni... » read more

6G Rollout Will Be A Patchwork At First


6G is expected to begin rolling out in 2030, but advances in 5G will inch cellular technology close enough that it will make the first 6G implementations seem more like just another upgrade. That's just the starting point, though. 6G technology gets much more interesting from there, connecting more devices at a significantly higher data rate, and enabling services that would be unattractive to ... » read more

Novel Assembly Approaches For 3D Device Stacks


The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

Mixed Messages Complicate Mixed-Signal


Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Distributing Intelligence Inside Multi-Die Assemblies


The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

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