category: Top Stories

category: Auto, Security & Edge AI

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

Disruptive Changes Ahead For Photomasks?
By Gregory Haley - 25 Jun, 2025 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down with four experts to explore the current state and future direction of mask-making, with insights from Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows ... » read more

EDA’s Top Execs Map Out An AI-Driven Future
By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Power Delivery Challenges For AI Chips
By Gregory Haley - 19 Jun, 2025 - Comments: 0

As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

Physics Limits Interposer Line Lengths
By Bryon Moyer - 19 Jun, 2025 - Comments: 1

Electrical interposers provide a convenient surface for mounting multiple chips within a single package, but even though interposer lines theoretically can be routed anywhere, insertion losses limit their practical length. Lines on interposers — and on silicon interposers in particular — can be exceedingly narrow. Having a small cross-section makes such lines resistive, degrading signals... » read more

Are Larger Reticle Sizes On The Horizon?
By Katherine Derbyshire - 19 Jun, 2025 - Comments: 0

Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

Can You Build A Known-Good Multi-Die System?
By Ed Sperling - 18 Jun, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss the challenges of designing and testing multi-die systems, including how to ensure they will work as expected, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadenc... » read more

Photomask Changes And Challenges At Mature And Advanced Nodes
By Gregory Haley - 16 Jun, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the current state and future direction of mask-making, with Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows are excerpts of that conversation.... » read more

RISC-V’s Increasing Influence
By Brian Bailey - 12 Jun, 2025 - Comments: 2

The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary to move forward gradually. Computer architectures and software have followed in the footsteps of processors developed 80 years ago. They aimed to solve sequential, scalar arithmetic problems usin... » read more

Multi-Die Assemblies Complicate Parasitic Extraction
By Ann Mutschler - 12 Jun, 2025 - Comments: 0

The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

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