category: Top Stories

category: IoT, Security & Automotive

Lines Blur Between Processor And Microcontroller
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Big changes are happening in the microcontroller market. That statement alone should give pause for most design engineers and raise their level of skepticism. In the past, microcontrollers were a steady business but not exactly an interesting one. That was before the big push toward “green” and the 65nm process node. And it was before vendors began adding logic and more fun... » read more

The Gleaning Power of Piezo
By Brian Fuller - 13 May, 2009 - Comments: 0

By Brian Fuller The inventor and green-tech missionary Trevor Baylis walked 100 miles across an African desert nearly 10 years ago to prove piezoelectric technology could power a cell phone. It was an interesting story that quickly faded from memory, as the technology was deemed clever but impractical. Enter Elizabeth Redmond and Andrew Katz, who have taken Baylis’ inspiration and piezo’s... » read more

Lower Power, Bigger Problems
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Low power used to be an afterthought in semiconductor design, and it almost was never a consideration in verification or manufacturability. But at each new process node, the number of power considerations goes up as the line widths go down. To begin with, there are two basic types of power. The first is dynamic, which has been a consideration ever since batteries were added int... » read more

Less Room For Error
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own. While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasing... » read more

Home Sweet (Power-Hogging) Home?
By Brian Fuller - 13 May, 2009 - Comments: 0

By Brian Fuller Numbers, history and technology are on a collision course inside your home. Consider the numbers: The big picture points to an even bigger opportunity for smart system design that can reduce power in and out of the chip. Since 1982, growth in peak demand for electricity has exceeded transmission growth by almost 25% every year. Yet spending on research and development �... » read more

How Many Power Islands Is Too Many?
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Power domains, also known as power islands, have become to design engineers what multiple cores are to processor architects. They can serve a purpose, namely reducing static current leakage and saving battery life. But they also can add so much complexity that they can make it almost impossible to get a new chip out the door. Just as there has been talk of hundreds of cores, th... » read more

Making Analog Easier
By Various Writers - 28 Apr, 2009 - Comments: 0

By Clive "Max" Maxfield I'm a digital design engineer by trade. All of those wibbly-wobbly effects that are characteristic of the analog domain make me nervous, and if something makes me nervous I tend to look the other way and hope it will go away. But analog isn’t going anywhere. On the contrary, the increasing amounts of analog/mixed-signal (AMS) functionality that feature in today's Sy... » read more

Intelligent Verification Offers Hope For “Smartening” Up Verification
By Cheryl Ajluni - 28 Apr, 2009 - Comments: 0

By Cheryl Ajluni As with death and taxes, when it comes to design some things are just inevitable. For one, as design geometries shrink, design complexity will continue to increase. For another, verification is the single most time-consuming and intensive part of the entire design cycle. While new tools and methodologies have enabled designers to work through many of the existing complexity i... » read more

Soft Errors Create Tough Problems
By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore. At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alter... » read more

Moore’s Law Splinters
By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Moore’s Law continues progressing at a rate of one node every two years or so, but the number of companies that are adhering to that schedule is becoming much harder to pinpoint. Even the nodes themselves are becoming fuzzy. While Intel is looking at 32nm as the next node after 45nm, TSMC is looking at 28nm as the next node after 40nm. And there are likely to be extensions wi... » read more

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