category: Top Stories

category: Auto, Security & Edge AI

Limits For TSVs In 3D Stacks?
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics. Stacking die holds the promise of becoming... » read more

Redefining Systems Around Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Engineers have been talking about system-level power budgets since Moore’s Law reached 65nm, but as power becomes a critical element of any design with or without a plug the definition of what constitutes a system is changing. While most SoC engineers think of the system as an IC, power increasingly is playing a significant role in the subsystem, and even in the larger syst... » read more

Low Power Drives Performance And TCO
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Pallab Chatterjee A common theme at this year’s Custom Integrated Circuit Conference was the reduction of power and power management while increasing data throughput. Historically, the show has featured new techniques for ultra high accuracy and brute force improvements in performance at all costs. The main theme this year was that in a world of mobile endpoint devices, the goal is to get... » read more

Thermal Modeling Held Back By Outdated Standards
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Energy Vs. Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler The terms power and energy are used almost interchangeably these days, but understanding and clearly articulating how to optimize embedded designs for maximum energy and power efficiency can make a big difference in a design. At a physics level, energy = power x time, whereas power is the rate of energy in a given time window. When the focus is specifically power, ... » read more

The Hidden Costs Of Test
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what’s less well known is that tests done improperly also can give false results, labeling good chips as bad�... » read more

Solid Verification Methodology Essential To Productivity
By Ann Mutschler - 22 Sep, 2011 - Comments: 0

Verifying SoCs from a functional perspective pushes the limits of already lean resources, driving verification teams to seek out new ways to improve productivity of verification tasks. Of course, with the verification task being a time-bound one, the challenge is daunting. It is well understood that consumer electronics is pushing the technology envelope in terms of the amount of technology ... » read more

Betting On Glass TSVs
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ed Sperling There are two big issues when it comes to through-silicon vias. One involves cost. The second involves heat—in particular, how to get heat out of a stacked die and what the thermal coefficient of the TSV will be to make sure it expands at a rate consistent with the SoCs in a package. To address these issues, System-Level Design caught up with Rao Tummala, professor of elect... » read more

High-Speed Interfaces Dominate New Designs
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Pallab Chatterjee Displays, inputs devices and storage interfaces have now moved up into the high-speed multi-gigabit per second data rates. These were formerly Mb/s technologies, but they have moved into the Gb/s format. Adding a high-speed interface on a system is not the same as on an IC. PCBs do not have the luxury of Moore's Law to drive the technology, so bringing new high-speed parts... » read more

20nm IP Portability Appears Virtually Impossible
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a ... » read more

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