category: Top Stories

category: Auto, Security & Edge AI

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

TSVs Ease Heat In 3D ICs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler In the evolving discussion of 3D ICs and through silicon via (TSV) technology, a key issue engineering teams are facing today is how to reduce the thermal coefficients between substrates in a stacked die. Simply put, what is the best way to get the heat out of the 2.5 or 3D IC? The answer, of course, is anything but simple. “In a 3D system, the heat hierarchy ... » read more

Solar Designs Focus On Low Power
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Pallab Chatterjee This year’s Semicon West showed growth in both attendees and exhibitors, but the big growth—at least from a percentage standpoint—was in the associated Intersolar show, which featured advances in PV and solar thermal systems. This year’s Intersolar show covered areas that were not just commercial grid-tied PV systems. Rather, it also had off-grid systems with ne... » read more

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Low Power Drives New Architectures
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Pallab Chatterjee Power became the driving discussion at several major events last month. The global cries for energy reduction, which have been mainstream since the early 1970s on the political level, have now moved to being real economic realities for component and systems suppliers. Chipmakers are finding that lower power makes good economic sense—lower cost of packaging, lower cost... » read more

More Analog Needed For Multicore SoCs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Mike Demler Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD ... » read more

Will Wide I/O Reduce Cache?
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

The Age Of No-Spin Doctors
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Pallab Chatterjee Solid-state flash memory still isn’t cheap, but performance, reliability and power have transformed it from a niche market into a mainstream one. And it’s about to get even more popular. At the recent flash memory summit, the majority of the sessions focused on the further penetration of NAND flash into the consumer electronics product segment. NAND technology alrea... » read more

Wide I/O’s Impact On Memory
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler Driven by the need to reduce power but increase bandwidth in smart phones and other mobile devices, system architects are grappling with new technologies to take system performance to the next level. Wide I/O, as well as some DDR technologies, are vying for center stage in tomorrow’s leading-edge mobile designs. “The big technological advancement that allows a ... » read more

Testing One, Two, Three
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ed Sperling The rule of thumb at 90nm—still one of the mainstream process nodes—has been that test is something you do when a chip is done. You attach electrodes on either side, make sure the signal comes through clearly, and that the SoC functions properly. Try the same thing at 40nm, with multiple power islands, multiple voltage rails, lots of third-party IP and usually a slew of p... » read more

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