Customer Perspective: STMicroelectronics


By Ed Sperling Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market. LPE: What do you see as the biggest changes ahead? Magarshack: One is the sheer size of the ecosy... » read more

Getting The Balance Right


Defining the power architecture for a low-power design means striking a balance between the high-level abstraction and measurements made typically at RTL and below, but today that is easier said than done. “The balance is that at the high level of abstraction, the design choices you make have a big effect over power, yet your ability to measure them is incomplete until you get much further... » read more

Dueling Power Formats


By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

Apache Update: Five Important Questions


By Ed Sperling It was supposed to be the first IPO since Magma went public in 2001. Instead, Apache was bought by Ansys in a deal that closed earlier this month—at a record pace for the EDA industry of less than two months since it was announced. So what exactly was behind the acquisition and why did Apache agree to sell? And what will become of Apache within the much larger Ansys? Low... » read more

What’s A Cell Phone?


By Ed Sperling Just because a smart phone is sold by Verizon or AT&T mobile no longer means that it will be used primarily as a phone. That distinction may sound trivial, but it has deep implications for the components that are used inside of these devices, how they’re used, and who wins the designs. Shifts such as this can also lead to broad changes in who buys the tools to develop the ... » read more

RF, MEMS, Photonics Driving 3D Stacking


By Pallab Chatterjee At Semicon West, a number of the key speakers and TechXPOTs were talking about current products being assembled and shipped with 3D technology. 3D die stacking is no longer a technology of the future. In fact it has been here for many years and has been used in millions, if not billions, of consumer, commercial and high-reliability designs. The two leading technologies ... » read more

3D Stacking: A Reality Check


By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks


In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

Bigger Pipes, New Priorities


By Ann Steffora Mutschler From the impact of stacking on memory subsystems to advances in computing architecture, Micron Technology is at the forefront in the memory industry. System-Level Design sat down to discuss challenges, as well as some possible solutions, that plague memory subsystem architects with Scott Graham, general manager for Micron’s Hybrid Memory Cube (HMC) and Joe Jeddeloh,... » read more

The Growing Need For A Systems Approach


By Gabe Moretti Electronic computing systems have gone through an evolutionary cycle since the invention of the mainframe, and the process is continuing. Semiconductor technology, mostly based on CMOS fabrication methods, has enabled an increase in design complexity and device functionality that have revolutionized the world. But 20nm processes may be the last that obey Newtonian physics. T... » read more

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