category: Top Stories

category: Auto, Security & Edge AI

Extending Battery Life
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling In the past it was all about clock frequency. People bought the latest computer and frequently paid a premium because it could crunch numbers faster. But as computing moves from the desktop into handheld devices, that focus is radically changing. Low-Power Engineering caught up with Mark Bohr, senior fellow and director of Intel’s process architecture and integration, to ta... » read more

Low Power: Coming To A CE Device Near You
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Pallab Chatterjee Low power and connectivity are the two pervasive design constraints for chips and systems being designed today, and they are showing up in devices that have not had architectural changes in decades. Some of the changes are customer-driven, some are consortia-driven, and international cooperation is making some of the regulatory-driven. The regulatory side is moving slow... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Customer perspective: STMicroelectronics
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Mutschler With eight SoC designs currently in development on its 28nm manufacturing process, STMicroelectronics is well acquainted with the power challenges of making those designs work. LPE discussed these issues with Philippe Magarshack, ST’s Technology R&D Group Vice-President. What follows are excerpts of that conversation. LPE: What are the biggest challenges in getting ST... » read more

One On One: ARM CTO Mike Muller
By Ed Sperling - 01 Jul, 2011 - Comments: 0

LPE: How far does Moore’s Law extend forward and what are we likely to encounter along the way? Muller: The good news is there is no known solution for 7nm. That implies that between now and then it’s okay. When I talk to people they seem fairly confident they’re going to get there. Exactly how they don’t know. Will there be any miracles needed? Yes, probably one or two. But 14nm and ... » read more

Let The Mobile Games Begin
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Pallab Chatterjee Mobile devices today are optimized for low- to mid-bandwidth data transmission, which is sufficient for e-mail, batch downloads of applications and music, and playback of encoded/compressed streaming video. But in coming months they will add another feature—image capture and processing and advanced graphics processing. This adds a whole new wrinkle to mobile devices, ... » read more

Different Ways To Boost Yield
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained. This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quick... » read more

IP Tagging Resurfaces
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling System-Level Design sat down with Kathy Werner, IP strategy and business manager inside of Freescale’s Design Technology Organization, to discuss tagging of soft IP. What follows are excerpts of that conversation. SLD: How new is the concept of IP tagging? Werner: IP tagging has been around for a long time. VSI Alliance was one of the first standards organizations that l... » read more

SoC Design In 5 Years
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different. At the center of this change are three very significant tr... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Skyrocketing software development costs, which for years have been “somebody else’s problem,” are now firmly part of the SoC development teams list of headaches. That has made virtual prototyping far more popular, particularly at 40nm and beyond, where engineers are looking at this approach as a way of managing complexity, doing architectural exploration and eve... » read more

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