Custom Substrates Save Assembly Time, Resources


Time-to-market (TTM) and performance are two of the most pressing issues in chip design and manufacturing. Designing devices for high-speed, high-performance applications requires immediate access to substrates so that product development can proceed quickly. Quick substrate access is also vital to validating intellectual property (IP) cores used in application-specific ICs (ASICs) – all of w... » read more

GPU Acceleration for Pixel-based Computing in Various Mask Processing and Verification Steps


A technical paper titled "Leaping into the curvy world with GPU accelerated O(p) computing" was published by researchers at D2S, Inc. The papers discusses the advantages of using GPU acceleration for pixel-based computing during various mask processing and verification steps.  It found that the O(p) approach for GPU acceleration is effective in handling data processing for curvy masks. F... » read more

A High-Capacity Solution for Power and Signal Integrity on 2.5D Silicon Interposers


The present trends in technology — such as increasing demand for computational power from CPUs and GPUs, connectivity driven by Internet of Things (IoT), data demands around connected and self-driving cars, and the design of processors optimized for artificial intelligence (AI) — require more functionality from integrated circuits. As designers struggle to find ways to scale with complexity... » read more

How Does Reclaiming Data Center Lost Capacity Result in Return on Investment?


As the importance of data center performance, efficiency, and sustainability grows, owners and operators must move beyond “quick fixes” when managing their data center and IT deployments. These temporary solutions are neither effective nor sustainable. Long-term solutions and effective management over time are required to achieve meaningful efficiency gains. Capacity planning is one such di... » read more

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software


PCI Express (PCIe) 5.0 silicon characterization across process, voltage, and temperature variations, is necessary for accelerating SoC designs. To measure key qualifying parameters, designers and test engineers must have a good understanding of the PCIe 5.0 base electrical specification and know the physical layer’s design architecture and features for accurate characterization of 32GT/s PHY ... » read more

Fundamentals of Power Amplifier Testing


The power amplifier (PA) – as either a discrete component or part of an integrated front end module (FEM) – is one of the most integral RF integrated circuits (RFICs) in the modern radio. In this application note, you will learn the basics of testing RF PAs and FEMs through an interactive application note with multiple how-to videos. When characterizing the performance of an RF PA, engin... » read more

Datacenter Chipmaker Achieves Double-Digit Power Reduction with Next-Gen Voltage Scaling


The Customer A fabless chipmaker making 5nm networking chips for datacenters. The Challenge High power consumption due to excessive voltage guard-bands What You'll Discover: Learn how the customer safely decreased the voltage from 650 mV to an average of 608 mV, resulting in a 12.5% dynamic power reduction. This significant optimization helped the chipmaker stand out as a low-pow... » read more

Advanced FTIR Optical Modeling for Hydrogen Content Measurements in 3D NAND Cell Nitride and Amorphous Carbon Hard Mask


Abstract Fourier Transform Infrared spectroscopy offers inline solutions for chemical bonding, epi thickness, and trench depth measurements. Through optical modeling of the transmission or reflectance spectra, information about the electronic structure and chemical composition may be obtained, which can be used for process control and monitoring. In this article, we demonstrate the measurement... » read more

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1


The PCI Express (PCIe) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. Find more inform... » read more

Gate Drive Configurations For GaN Power Transistors


This whitepaper gives a compact overview of the recommended gate drive concepts for both GIT (gate injection transistor) and SGT (Schottky gate transistor) product families. A versatile standard drive (RC interface) can be easily adapted to both technologies. The document also provides basic gate drive dimensioning guidelines and some typical application examples. Find more information here. » read more

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