Bridging the Gap Between Industry and Academia

By Cadence - 24 Apr, 2024 - Comments: 0

The purpose of the Cadence Academic Network is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence in the areas of verification, design, and implementation of microelectronic systems. Taking a four-pronged approach of recruiting, promoting the Cadence university software program, establishing academic p... » read more

Rigorous Correlation Methodology for PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models

By Alphawave Semi - 24 Apr, 2024 - Comments: 0

IBIS-AMI models have been around for a decade and evolved to provide off-chip and system designers an efficient way to assess link performance of high-speed electrical interfaces with transceivers implementing various combination of equalization techniques [1]. As with any model, for IBIS-AMI to be useful they need to be benchmarked and carefully correlated to real-world silicon performance of ... » read more

How To Scale Application Security Across The Enterprise

By Synopsys - 24 Apr, 2024 - Comments: 0

Enterprise organizations have hundreds of developers on numerous teams in dozens of business units. They are all working on thousands of applications, releasing software in very rapid iteration cycles. The challenges of development across all these software development life cycles, business units, and organizational silos are well known, and the sheer scale of enterprise development multiplies ... » read more

Aeonic Generate GGM High Performance SoC Clock Generation Module

By Movellus - 24 Apr, 2024 - Comments: 0

Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

IC Compiler II: Finding The Best Floorplan, Fast

By Synopsys - 17 Apr, 2024 - Comments: 0

As designers strive to pack more and more functionality into todays’ SoC’s, design size (in terms of the number of transistors packed into a chip) is growing almost exponentially. This growth brings with it an unbounded increase in not just the technical complexity of performing the physical layout of the design due to capacity challenges, but also requires designers to make choices that ca... » read more

A Vision For Electronics Supply Chain Management

By SEMI - 17 Apr, 2024 - Comments: 0

Supply chain disruptions and chip shortage have become household terms in recent times. COVID-19 highlighted the vulnerability of supply chains of countless industries and their critical role in the global economy. Companies across the electronics manufacturing value chain have been affected. At last count, the semiconductor shortage has already cost the automotive industry alone over $150 bill... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

By eBeam Initiative - 17 Apr, 2024 - Comments: 0

How Advantest Corporation, ASML, Fraunhofer, imec, Siemens EDA and others are using deep learning in semiconductor manufacturing. Click here to read more. » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development

By Coventor - 17 Apr, 2024 - Comments: 0

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

Unlocking PPA Benefits of Backside Routing

By Synopsys - 10 Apr, 2024 - Comments: 0

The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control

By Arm - 10 Apr, 2024 - Comments: 0

High-performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies. An effective prefetching mechanism can improve cache hit rate significantly. Data prefetching boosts the execution performance by fetching data before it is needed. While prefetching improves performance substantially on many programs, it can significantly red... » read more

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category: Whitepapers

category: IoT, Security & Automotive

Bridging the Gap Between Industry and Academia

Rigorous Correlation Methodology for PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models

How To Scale Application Security Across The Enterprise

Aeonic Generate GGM High Performance SoC Clock Generation Module

IC Compiler II: Finding The Best Floorplan, Fast

A Vision For Electronics Supply Chain Management

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development

Unlocking PPA Benefits of Backside Routing

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control

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