Engineering Simulation Workloads And The Rise of the Cloud


Cloud service providers (CSPs) continue to improve the performance capabilities of their non-accelerated and accelerated compute instances, as well as augment their HPC infrastructure with domain-area expertise of targeted HPC workloads. Additionally, engineers, researchers, and scientists are becoming more comfortable with the types of workloads that can be run in the cloud within acceptable w... » read more

Achieving Your Low Power Goals With Synopsys Ultra Low Leakage IO


The demand for low power design has intensified with shrinking geometries. At the same time, innovation in battery operated, handheld devices has increased the design complexity by adding more and more functionality. The focus is on power-optimized designs while maintaining low cost and reduced risk. Designers face these complex and contradictory challenges: developing products with the lowest ... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation


As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe... » read more

Detection Of Contaminants In Positive And Negative Ion Mode Using In-line SIMS With An Oxygen Primary Ion Beam


Utilizing Secondary Ion Mass Spectrometry (SIMS) for in-line metrology is a newly emerging method of process control that requires contamination-free measurements, enabling SIMS on product wafers. SIMS measurements of negative ions are usually associated with a Cesium primary ion beam. Unfortunately, when Cesium is present in Silicon, it forms trap states in the Si band gap, which can cause ser... » read more

Automotive Safety Island


The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. Automotive ICs, once deployed for simple functions like controlling windows, are now performing complex functions related to advanced driver-assist systems (ADAS) and autonomous driving applications. The processing power required results in very large and complex ICs that ... » read more

Performance Benchmarking Embedded FPGAs


This Application Note has the following objectives: Provide performance benchmark achievable on the various EFLX IP Cores currently available; Provide performance variation for different process nodes; Provide performance benchmarks to compare with other embedded FPGAs. Click here to read more. » read more

Accelerating Coverage Closure With AI-Based Verification Space Optimization


Coverage is at the heart of all modern semiconductor verification. There is no maxim more fundamental to this process than “if you haven’t exercised it, you haven’t verified it.” Although covering a particular aspect of a chip design does not guarantee that all bugs are found — bug effect propagation and checker quality are also key factors — it is certainly true that bugs cannot po... » read more

From Data Center To End Device: AI/ML Inference With GDDR6


Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inference. As inference migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be incre... » read more

Driving Performance In GaN-Based USB-C Adapters And Chargers With EPR


With the announcement of the USB PD 3.1 standard [1], higher power levels of up to 240 W are enabled. Still, the wide output voltage range from 5 V to 48 V raises new challenges for the converter topologies currently in use. In this white paper, the combination of an AC-DC PFC boost and a DC-DC hybrid flyback (HFB) stage [2], also well known as asymmetrical half-bridge flyback topology, is prop... » read more

Pre-Layout, Post-Layout Circuit Reliability


With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability... » read more

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