Power Methodology For Estimation And Optimization In The ASIC/SoC Flow


In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

Optimize 5G New Radio MIMO Test And Debug


Radio technology is evolving from single antenna transmit-receive communication systems to multiple-input multiple-output (MIMO) antenna communication systems. MIMO technology is a wireless communication technique for sending and receiving multiple data signals simultaneously over the same radio channel. MIMO techniques play a prominent role in Wi-Fi communications, as well as in 4G long-term e... » read more

Timing Accuracy For eCPRI Fronthaul And Open RAN


Open RAN is an eCPRI-based open fronthaul interface between the radio unit (RU) and distributed unit (DU) [1]. This white paper discusses timing accuracy for eCPRI fronthaul transport networks. The eCPRI interface is supported by packet switched fronthaul transport networks. When the fronthaul network is used to synchronize an eCPRI node, it must provide timing at the user network interface acc... » read more

Machine Learning-Driven Full-Flow Chip Design Automation


To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning computer science, the next chip design automation revolution is now possible. The Cadence® Cerebrus™ Intelligent Chip Explorer utilizes both of these technologies, based o... » read more

A Novel Photosensitive Permanent Bonding Material Designed For Polymer/Metal Hybrid Bonding Applications


Wafer-level hybrid bonding techniques, which provide simultaneous bonding between metal-metal and dielectric-dielectric layers, have attracted more attention in recent years for fabricating 3D integrated circuits with high bandwidth and high interconnect density. However, there are some issues for conventional hybrid bonding using silicon oxide as the dielectric, such as the high stress and low... » read more

Verifying A DDR5 Memory Subsystem


With the increasing complexity of DDR memory models and a vast set of configurations, it has become a daunting experience for verification engineers to verify memory subsystems. With the help of DDR5 Questa VIP and its unique features, engineers can maximize their debugging capabilities and achieve their verification goals quickly and efficiently. This paper introduces the Siemens EDA DDR5 and ... » read more

Synchronization Overview And Case Study on Arm Architecture


The objective of this white paper is to share knowledge on Arm architecture. The target reader of this document is those who work on synchronization with the Arm architecture. [Warning] When we are dealing with locking optimizations, we must be extremely careful about correctness. Bugs caused by synchronization are usually hard to root cause and the optimized code may crash on other CPUs wit... » read more

Authenticating Batteries Before Rapid And Fast Charging


If asked, most consumers will complain about the battery life of their smartphone. In reality, this is more a charging issue since, with traditional charging solutions, even a couple of hours of charging can result in a minimal improvement in charge on some handsets. Smartphone manufacturers are differentiating their offering by providing fast or rapid charging solutions. However, this places t... » read more

Compute Express Link (CXL): All You Need To Know


An in-depth look at Compute Express Link  (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. We discuss how CXL technology maintains memory c... » read more

Fidelity Pointwise Grid Cell Remediation Method For Overset Meshes


In computational fluid dynamics, (CFD) overset meshing is highly appreciated in turbomachinery for moving body applications. Moreover, significant efforts have been made to improve the overset flow solver capability, but only limited developments have been made to what is quickly becoming a bottleneck in the simulation process — the creation of the overset composite grid. Cadence Fidelity Poi... » read more

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