Accelerating Artificial Intelligence Innovation With Concurrent Design Engineering


Artificial intelligence (AI) is transforming every industry and creating new demands for computing performance, efficiency, and scalability. Designers are creating and deploying AI-dedicated chips to meet these challenges and enable faster and smarter applications across various domains, such as cloud, edge, mobile, automotive, and the Internet of Things (IoT). However, designing AI chips is no... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier


In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

Heterogenous Integration Expertise for Sensors and MEMS Packaging and Assembly


Sensors and microelectromechanical systems (MEMS) are unlocking new design possibilities for miniature devices used in healthcare, smart systems, consumer electronics, and more. Designers need a partner experienced with Heterogenous Integration (HI) to assemble the unique components for these devices and address the complications of these integrations. In this white paper, you will learn: ... » read more

Deploying Generative AI At Scale With Flexibility And Speed


As the types of content that generative AI (GenAI) can process expands to advanced video, images, audio, and text, the race to innovate is creating new hurdles for developers. Discover how to overcome the challenges surrounding scalability and speed of GenAI development to offer cutting-edge experiences. Read more here and learn: How to run and scale GenAI workloads efficiently. Tech... » read more

Verifying SRAM Yield Inclusive Of Rare And Random Defects


Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This work presents a novel method to enable the inclusion of ... » read more

Automotive Design: How AI Is Transforming The Art Of Simulation


The automotive sector is about to experience a major wave of innovation as artificial intelligence (AI) is applied to design simulation, according to experts. The technology makes it possible to reduce the time needed to run the analyses for crash-test simulations — one of the most data-heavy exercises in automotive design — from several days to minutes. Read more here to learn about a p... » read more

ESD Verification For 2.5D And 3D-ICs


Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

Lower Your Power Consumption For Battery-Operated Smart Devices


Striking the right balance between battery life and customer experience The number of connected smart home battery-operated devices is expected to grow as consumers look for new ways to retrofit their homes with IoT devices without power cabling. This change leaves device makers in search of new ways to make their battery-operated smart home products more power-efficient at all levels, while st... » read more

Innovations In Distributed Functional Safety


Innovations in hardware functional safety will be available in future safety-critical products from Imagination. These patent-pending techniques are for processing cores which require Automotive Safety Integrity Level (ASIL)-B levels of protection while incurring the smallest possible area, power and performance costs. This paper outlines new Distributed Safety Mechanisms (DSMs) for CPU and ... » read more

SRAM PUF – The Secure Silicon Fingerprint


For many years, silicon Physical Unclonable Functions (PUFs) have been seen as a promising and innovative security technology making steady progress. Today, Static Random-Access Memory (SRAM)-based PUFs have been deployed in hundreds of millions of devices and offer a mature and viable security component that is achieving widespread adoption in commercial products. They are found in devices ran... » read more

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