category: Whitepapers

category: IoT, Security & Automotive

Microchip Sees Significant Productivity Gains In Mature-Node Custom IC Design With In-Design Signoff DRC
By Siemens EDA - 27 Oct, 2021 - Comments: 0

Microsemi pioneered the design of innovative chips that are used for multiple purposes across a variety of industries, using both mature and advanced process nodes. In mature node custom design implementation, layout designers still spend a significant amount of their valuable time fixing DRC errors—time that could be more beneficially spent ensuring their designs meet their PPA goals. By rep... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers
By Synopsys - 27 Oct, 2021 - Comments: 0

Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Hierarchical Verification for EC-FPGA Flow
By OneSpin Solutions - 27 Oct, 2021 - Comments: 0

This document describes the methodology to apply EC-FPGA verification using hierarchical netlists. This approach is recommended in case the verification of the overall design has issues with convergence. The document contains a step-by-step description of different methods while providing reasoning for the soundness of each approach. It is assumed for this document that the reader is familiar w... » read more

3D-IC Design Challenges And Requirements
By Cadence - 27 Oct, 2021 - Comments: 0

As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design and packaging teams are taking a close look at vertical stacking multiple chips and chiplets. This technology, called 3D-IC, promises many advantages over traditional single-die planar designs. Some are using the term “More-than-Moore” to describe the potential of this new technology. Integratio... » read more

High Thermal Die-Attach Paste Development For Analog Devices
By Amkor - 20 Oct, 2021 - Comments: 0

Authors: Kiichiro Higaki, Toru Takahashi, Akinori Ono from Assembly Engineering Department Amkor Technology Japan, Inc. Keiichi Kusaka, Takayuki Nishi, Takeshi Mori from Information & Telecommunication Materials Research Laboratory, Sumitomo Bakelite Company, Limited Daisuke Koike, Masahiko Hori from Package Solution Technology Development Department, Electronic Devices & Storage Res... » read more

Bringing Intelligent Headlamps To Light via Simulation
By Ansys - 13 Oct, 2021 - Comments: 0

Once seen as a basic, utilitarian product feature, today automotive headlamps are becoming much more innovative — and a critical source of competitive differentiation. Intelligent headlamps, which autonomously produce adaptive light beams, are capturing the imagination of the world’s automakers and consumers alike. But how can automotive engineering teams verify the performance of their com... » read more

Introducing mPower
By Siemens EDA - 13 Oct, 2021 - Comments: 0

Power integrity analysis evaluates circuits to determine if they will provide their designed/intended performance and reliability as implemented. Designers must be able to verify analog and digital power integrity from the RTL/gate-level through die-level integrations up to the package and board system-level. The mPower toolset is an innovative power integrity verification solution that brings ... » read more

How Semiconductor Solutions Address Safety Requirements Of Future Power Distribution Networks In Autonomous Vehicles
By Infineon - 13 Oct, 2021 - Comments: 0

Open up the bonnet of any modern automobile and many of us would be hard-pressed to find anything that we could fix ourselves. With pipes and cables almost artistically integrated into the engine bay, and sleek plastic covers fitted everywhere, there is very little that can still be recognized, yet alone repaired. Perhaps the only location where we feel comfortable is the “fuse box”, or pow... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences
By Various Writers - 13 Oct, 2021 - Comments: 0

Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

Manage Scaling Challenges For Silicon Success
By Siemens EDA - 12 Oct, 2021 - Comments: 0

Semiconductor companies are faced with significant challenges related to technology scaling, design scaling, and system scaling. These challenges have a broad impact on design development, manufacturing, and functional operation. This paper discusses the challenges and the specific impact of a Silicon Lifecycle Solutions approach that includes DFT, operations, and Embedded Analytics in enabling... » read more

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