Working With RISC-V

By Ed Sperling - 17 Aug, 2021 - Comments: 0

RISC-V is coming on strong, but working with this open-source processor core isn't as simple as plugging in a commercial piece of IP. Zdenek Prikryl, CTO at Codasip, talks about utilizing hypervisors and open source tools and extensions to the RISC-V instruction set architecture, where design teams can run into problems, what will change as the architecture becomes more mature, the difference b... » read more

EDA In The Cloud

By Ann Mutschler - 09 Jun, 2021 - Comments: 0

Hagai Arbel, CEO of Vtool, talks with Semiconductor Engineering about the benefits of moving EDA tools to the cloud, why it has been slow to take off, and what will drive this trend in the future. » read more

Next-Gen SerDes Roadmap

By Ed Sperling - 25 May, 2021 - Comments: 0

An explosion in data is causing a series of successive bottlenecks in the data center. Priyank Shukla, product marketing manager for high-speed SerDes IP at Synopsys, digs into the performance roadmap for moving data within server racks and between different racks, where the bottlenecks are today, and how they will be addressed in the future. Related SerDes Knowledge Center Top stories... » read more

Next-Gen Design Challenges

By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Better Quality RTL

By Ann Mutschler - 02 Feb, 2021 - Comments: 0

How do you measure the quality of RTL? Philippe Luc, director of verification at Codasip, talks about identifying bugs, improving the overall quality of the verification, what happens when different blocks are used in a design, and how to improve efficiency in the verification process. » read more

High-Speed SerDes At 7/5nm

By Ed Sperling - 02 Jun, 2020 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

Rising Packaging Complexity

By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

Speeding Up Verification Using SystemC

By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Timing Closure At 7/5nm

By Ed Sperling - 17 Mar, 2020 - Comments: 2

Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

Banking On FPGA Prototyping

By Ed Sperling - 04 Mar, 2020 - Comments: 0

Juergen Jaeger, product management director at Cadence, explains how FPGA prototyping can improve efficiency and reduce design costs, what the development costs are for various phases of the design flow, how that changes across different markets such as automotive and 5G, and why software is now the biggest knob to turn for reducing cost and time to market. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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