Fusing Implementation And Verification

By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

Speeding Up FPGA Development

By Ed Sperling - 28 Feb, 2020 - Comments: 0

Salaheddin Hetalani, field application engineer at OneSpin Solutions, talks about why it’s getting harder to design and debug FPGAs, how much design time can be saved through formal techniques, and why just relying on programmability isn’t the most efficient approach. » read more

Hybrid Prototyping

By Ed Sperling - 26 Feb, 2020 - Comments: 1

David Svensson, applications engineer in Synopsys’ Verification Group, explains how a virtual transaction logic model can be connected to develop hardware-dependent drivers before RTL actually exists, why this is now critical for large, complex designs, and how to find the potential bottlenecks and debug both software and hardware. » read more

Why Is PSS So Important?

By Ed Sperling - 25 Feb, 2020 - Comments: 0

Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save. » read more

EDA In The Cloud

By Ed Sperling - 18 Feb, 2020 - Comments: 0

Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Ensuring Coverage In Large SoCs

By Ed Sperling - 04 Feb, 2020 - Comments: 0

Sven Beyer, product manager for design verification at OneSpin Solutions, talks about why formal technology is required to ensure coverage in some of the newest chips, how it deals with potential interactions and different use cases, and why it is gaining traction in automotive applications. » read more

Context-Aware Debug

By Ed Sperling - 31 Jan, 2020 - Comments: 0

Moses Satyasekaran, product manager at Mentor, a Siemens Business, examines the growing complexity of debug, which now includes software, power intent and integration, multiple clocking and reset domains, and much more, where the limitations are for debug, and how automotive, functional safety and mixed signal affect the overall process. » read more

Analog Simulation At 7/5/3nm

By Ed Sperling - 27 Jan, 2020 - Comments: 0

Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

Dealing With ECOs In Complex Designs

By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Distributed Design Implementation

By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

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Knowledge Centers
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