Benchmarking ultra-low-power μNPUs; pSRAM bitcell for high-speed; connected vehicles security; HW security verification; contact layer attributes; RISC-V cache architecture; multi-die floorplanning.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Benchmarking Ultra-Low-Power μNPUs | Imperial College London and University of Cambridge |
| Security Risks and Designs in the Connected Vehicle Ecosystem: In-Vehicle and Edge Platforms | Università di Pisa, Ford Motor Company, MIT, and the Institute of Informatics and Telematics |
| PPAC Driven Multi-die and Multi-technology Floorplanning | Texas A&M University and Duke University |
| ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification | University of Florida |
| Thermal Slip Length at a Liquid/Solid Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer | Caltech, T. J. Watson Sr. Lab of Applied Physics |
| Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems | University of Wisconsin–Madison, USC and GlobalFoundries |
| ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions | Politecnico di Torino and EPFL |
Find more semiconductor research papers here.
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